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MP28248 Datasheet(PDF) 12 Page - Monolithic Power Systems

Part No. MP28248
Description  High-Efficiency, Fast-Transient, 3A, 4.2V-20V Input Synchronous Step-down Converter in a QFN12 (2x3mm) Package
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Maker  MPS [Monolithic Power Systems]
Homepage  http://www.monolithicpower.com
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MP28248 Datasheet(HTML) 12 Page - Monolithic Power Systems

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MP28248 – 3A, 3.3V-20V INPUT, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER IN 2X3MM QFN
MP28248 Rev. 1.0
www.MonolithicPower.com
12
1/5/2012
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
BST
N1
LSG
VCC
C3
SW
L
COUT
C5
Figure 4: Floating Driver and Bootstrap Charging
The floating power MOSFET driver is powered by
an external bootstrap capacitor. This floating
driver has its own UVLO protection with a rising
threshold of 2.2V and a hysteresis of 150mV.
The bootstrap capacitor is charged from VCC
through N1 (Figure 4). N1 turns on when the LS-
FET turns on and turns off when the LS-FET
turns off.
Switching Frequency
MP28248 uses constant-on-time control because
there is no dedicated oscillator in the IC. The
input voltage is feed-forwarded to the on-time
one-shot timer through the resistor R7. The duty
ratio is kept as VOUT/VIN, and the switching
frequency is fairly constant over the input voltage
range.
The
switching
frequency
can
be
determined with the following equation:
6
SW
7IN
DELAY
IN
OUT
10
f (kHz)=
9.3 R (kΩ)V (V)
+t
(ns)
V (V)-0.4
V
(V)
(3)
Where tDELAY is the comparator delay, and equals
approximately 40ns.
MP28248 is optimized to operate at high
switching frequency with high efficiency. High
switching frequency makes it possible to use
small-sized LC filter components to save system
PCB space.
Jitter and FB Ramp Slope
Jitter occurs in both PWM and skip modes when
the noise in the VFB ripple propagates a delay to
the HS-FET driver, as shown in Figure 5 and
Figure 6. Jitter can affect system stability, with
noise immunity proportional to the steepness of
VFB’s downward slope. However, VFB ripple does
not directly affect noise immunity.
V
RE F
V
FB
HS D river
VNOISE
J itter
V
S L O PE1
Figure 5: Jitter in PWM Mode
V
FB
HS D river
Jitter
V
REF
V
SL O P E 2
VNOISE
Figure 6: Jitter in Skip Mode
Ramp with Large ESR Capacitor
For POSCAP or other types of capacitors with
large ESR as the output capacitors, the ESR
ripple dominates the output ripple, and the slope
on the FB is related to the ESR. Figure 7 shows
an equivalent circuit in PWM mode with the HS-
FET off and without an external ramp circuit. Go
to the application information section for design
recommendations for large ESR capacitors.
Figure 7: Simplified Circuit in PWM Mode without
External Ramp Compensation
To realize a stable output without an external
ramp, select an ESR value using the following
equation:

SW
ON
ESR
OUT
tt
0.7
2
R
C
(4)
Where tSW is the switching period.


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