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ISPLSI2128VE-135LT100 Datasheet(PDF) 7 Page - Lattice Semiconductor |
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ISPLSI2128VE-135LT100 Datasheet(HTML) 7 Page - Lattice Semiconductor |
7 / 20 page Specifications ispLSI 2128VE 7 Internal Timing Parameters1 Over Recommended Operating Conditions tio 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros. Table 2-0036A/2128VE v.1.0 Inputs UNITS DESCRIPTION # 2 PARAMETER 20 Input Buffer Delay ns tdin 21 Dedicated Input Delay ns tgrp 22 GRP Delay ns GLB t1ptxor 25 1 Product Term/XOR Path Delay ns t20ptxor 26 20 Product Term/XOR Path Delay ns txoradj 27 XOR Adjacent Path Delay ns tgbp 28 GLB Register Bypass Delay ns tgsu 29 GLB Register Setup Time before Clock ns tgh 30 GLB Register Hold Time after Clock ns tgco 31 GLB Register Clock to Output Delay ns 3 tgro 32 GLB Register Reset to Output Delay ns tptre 33 GLB Product Term Reset to Register Delay ns tptoe 34 GLB Product Term Output Enable to I/O Cell Delay ns tptck 35 GLB Product Term Clock Delay ns ORP tob 38 Output Buffer Delay ns tsl 39 Output Slew Limited Delay Adder ns GRP t4ptbpc 23 4 Product Term Bypass Path Delay (Combinatorial) ns t4ptbpr 24 4 Product Term Bypass Path Delay (Registered) ns torp 36 ORP Delay ns torpbp 37 ORP Bypass Delay ns Outputs toen 40 I/O Cell OE to Output Enabled ns todis 41 I/O Cell OE to Output Disabled ns tgoe 42 Global Output Enable ns tgy0 43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) ns tgy1/2 44 Clock Delay, Y1 or Y2 to Global GLB Clock Line ns Clocks tgr 45 Global Reset to GLB -180 MIN. MAX. 0.5 1.1 0.6 3.4 3.4 3.4 0.0 — — 0.3 0.6 4.3 5.9 4.0 1.6 2.0 1.9 2.4 1.4 0.4 3.0 3.0 2.0 1.2 1.4 4.4 — — — — — — — 1.2 2.3 — — — — 1.0 — — — — — — — — — 1.2 1.4 — -250 MIN. MAX. 0.5 0.7 0.2 2.8 2.8 2.8 0.0 — — 0.2 0.3 3.7 2.9 3.6 1.4 2.0 1.5 2.0 1.1 0.4 2.4 2.4 1.6 1.0 1.2 3.9 — — — — — — — 0.8 1.7 — — — — 0.8 — — — — — — — — — 1.0 1.2 —ns Global Reset |
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