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APA075 Datasheet(PDF) 11 Page - Microsemi Corporation |
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APA075 Datasheet(HTML) 11 Page - Microsemi Corporation |
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11 / 174 page  ProASICPLUS Flash Family FPGAs v5.2 1-7 Note: This figure shows routing for only one global path. Figure 1-7 • High-Performance Global Network Table 1-1 • Clock Spines APA075 APA150 APA300 APA450 APA600 APA750 APA1000 Global Clock Networks (Trees) 4 4 4 4 4 4 4 Clock Spines/Tree 6 8 8 12 14 16 22 Total Spines 24 32 32 48 56 64 88 Top or Bottom Spine Height (Tiles) 16 24 32 32 48 64 80 Tiles in Each Top or Bottom Spine 512 768 1,024 1,024 1,536 2,048 2,560 Total Tiles 3,072 6,144 8,192 12,288 21,504 32,768 56,320 Top Spine Bottom Spine Global Pads Global Pads Global Networks Global Spine Global Ribs High-Performance Global Network Scope of Spine (Shaded area plus local RAMs and I/Os) PAD RING PAD RING |
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