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P1AFS15002 Datasheet(PDF) 11 Page - Microsemi Corporation

Part No. P1AFS15002
Description  Terrestrial FPGA and SoC Product Catalog
Download  27 Pages
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Manufacturer  MICROSEMI [Microsemi Corporation]
Direct Link  http://www.microsemi.com
Logo MICROSEMI - Microsemi Corporation

P1AFS15002 Datasheet(HTML) 11 Page - Microsemi Corporation

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www.microsemi.com/soc
ProASIC3 nano
The lowest-cost solution with enhanced I/O capabilities
Microsemi’s innovative ProASIC3 nano devices bring a new level of value and flexibility to high-volume markets. When measured against the typical project
metrics of performance, cost, flexibility and time-to-market, ProASIC3 nano devices provide an attractive alternative to ASICs and ASSPs in fast moving or highly
competitive markets. Customer-driven total system cost reduction was a key design criterium for the ProASIC3 nano program. Reduced device cost, availability of
known good die, a single-chip implementation and a broad selection of small footprint packages all contribute to lower total system costs.
• 1.5Vcoreforlowpower
• Knowngooddiesupported
• 350MHzsystemperformance
• EmbeddedSRAMNVM
• Configurationmemoryerrorimmune
• Enhancedcommercialtemperature
• EnhancedI/Ofeatures
• ISPandsecurity
• Reprogrammableflashtechnology
• Zerolead-timeonselecteddevices
• CCCsandPLLs
I/Os Per Package
ProASIC3 nano Devices
ProASIC3 nano Devices
A3PN010
A3PN020
A3PN060
A3PN125
A3PN250
System Gates
10,000
20,000
60,000
125,000
250,000
Typical Equivalent Macrocells
86
172
512
1,024
2,048
VersaTiles(D-flip-flops)
260
520
1,536
3,072
6,144
RAM1(1,024bits)
18
36
36
4,608-BitBlocks1
4
8
8
FlashROMKbits(1,024bits)
1
1
1
1
1
AES-Protected ISP1
Yes
Yes
Yes
Integrated PLL in CCCs1
1
1
1
VersaNetGlobals
4
4
18
18
18
I/OBanks
2
3
2
2
4
Maximum User I/Os (packaged device)
34
49
71
71
68
Known Good Die User I/Os
34
52
71
71
68
Package Pin
QN
VQ
QN48
QN68
VQ100
VQ100
VQ100
ProASIC3 nano Devices
A3PN010
A3PN020
A3PN060
A3PN125
A3PN250
Known Good Die
34
52
71
71
68
QN48
34
QN68
49
VQ100
71
71
68
Notes:
1. A3PN030 and smaller devices do not support this feature.
2. For higher densities and support of additional features, refer to the ProASIC3 and ProASIC3E datasheets and FPGA fabric user’s guides.


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