4 www.microsemi.com/soc

SmartFusion

The customizable system-on-chip (cSoC) device

protection and ease-of-use. Based on Microsemi’s proprietary flash process, SmartFusion cSoCs are ideal for hardware and embedded designers who need a true

system-on-chip that gives more flexibility than traditional fixed-function microcontrollers without the excessive cost of soft processor cores on traditional FPGAs.

• Availableincommercial,industrial

and military* grades

• Hard100MHz32-bitARM

Cortex-M3 CPU

• Multi-layerAHBcommunications

matrixwithupto16Gbpsthroughput

• 10/100EthernetMAC

• Twoperipheralsofeachtype:

• Upto512KBflashand

64KBSRAM

• Externalmemorycontroller(EMC)

• 8-channelDMAcontroller

• Integratedanalog-to-digital

converters (ADCs) and digital-

to-analog converters (DACs)

with1percentaccuracy

• On-chipvoltage,currentand

temperature monitors

• Uptoten15nshigh-speed

comparators

• Analogcomputeengine(ACE)

offloadsCPUfromanalog

processing

• Upto35analogI/Osand

169digitalGPIOs

* Under development

SmartFusion Devices

Notes:

1. Not available on A2F500 for the PQ208 package.

2. Two PLLs are available in CS288 and FG484 (one PLL in FG256 and PQ208).

3. These functions share I/O pins and may not all be available at the same time.

4. Available on FG484 only. PQ208, FG256, and CS288 packages offer the same programmable analog capabilities as A2F200.

Notes:

1. These pins are shared between direct analog inputs to the ADCs and voltage/current/temperature monitors.

2. 16 MSS I/Os are multiplexed and can be used as FPGA I/Os, if not needed for the MSS. These I/Os support Schmitt triggers and support only LVTTL and LVCMOS (1.5 / 1.8 / 2.5, 3.3 V) standards.

3. 9 MSS I/Os are primarily for 10/00 Ethernet MAC and are also multiplexed and can be used as FPGA I/Os if Ethernet MAC is not used in a design. These I/Os support Schmitt triggers and support only LVTTL and LVCMOS

(1.5 / 1.8 / 2.5, 3.3 V) standards.

4. 10/100 Ethernet MAC is not available on A2F060.

5. EMC is not available on the A2F500 PQ208 package.

Package I/Os: MSS + FPGA I/Os

SmartFusion Devices

A2F060

A2F200

A2F500

FPGA Fabric

System Gates

60,000

200,000

500,000

Tiles (D-flip-flops)

1,536

4,608

11,520

RAM Blocks (4,608 bits)

8

8

24

Microcontroller

Subsystem (MSS)

Flash (Kbytes)

128

256

512

SRAM (Kbytes)

16

64

64

Cortex-M3 with

Memory Protection Unit (MPU)

Yes

Yes

Yes

10/100 Ethernet MAC

No

Yes

Yes

External Memory Controller (EMC)

24-bit address, 16-bit data

24-bit address, 16-bit data

DMA

8 Ch

8 Ch

8 Ch

I2C

2

2

2

SPI

2

2

2

16550 UART

2

2

2

32-Bit Timer

2

2

2

PLL

1

1

32 KHz Low Power Oscillator

1

1

1

100 MHz On-Chip RC Oscillator

1

1

1

Main Oscillator (32 KHz to 20 MHz)

1

1

1

Programmable

Analog

ADCs (8-/10-/12-bit SAR)

1

2

DACs (12-bit sigma-delta)

1

2

Signal Conditioning Blocks (SCBs)

1

4

2

8

1

4

1

4

2

8

Device

A2F060

A2F200

A2F500

TQ144

CS288

FG256

PQ208

CS288

FG256

FG484

PQ208

CS288

FG256

FG484

Direct Analog Input

11

11

11

8

8

8

8

8

8

8

12

4

4

4

16

16

16

16

16

16

16

20

Total Analog Input

15

15

15

24

24

24

24

24

24

24

32

Total Analog Output

1

1

1

1

2

2

2

1

2

2

3

22

31

25

41

22

31

25

41

FPGA I/Os

33

68

66

66

78

66

94

78

66

128

Total I/Os

70

112

108

113

135

117

161

113

135

117

204