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AD7712ANZ Datasheet(PDF) 19 Page - Analog Devices |
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AD7712ANZ Datasheet(HTML) 19 Page - Analog Devices |
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19 / 28 page  REV. F AD7712 –19– Table VI. Calibration Truth Table Cal Type MD2, MD1, MD0 Zero-Scale Cal Full-Scale Cal Sequence Duration Self-Cal 0, 0, 1 Shorted Inputs VREF One-Step 9 1/Output Rate System Cal 0, 1, 0 AIN – Two-Step 4 1/Output Rate System Cal 0, 1, 1 – AIN Two-Step 4 1/Output Rate System Offset Cal 1, 0, 0 AIN VREF One-Step 9 1/Output Rate Background Cal 1, 0, 1 Shorted Inputs VREF One-Step 6 1/Output Rate Span and Offset Limits Whenever a system calibration mode is used, there are limits on the amount of offset and span that can be accommodated. The range of input span in both the unipolar and bipolar modes for AIN1 has a minimum value of 0.8 VREF/GAIN and a maxi- mum value of 2.1 VREF/GAIN. For AIN2, both numbers are a factor of 4 higher. The amount of offset that can be accommodated depends on whether the unipolar or bipolar mode is being used. This offset range is limited by the requirement that the positive full-scale calibration limit is ≤ 1.05 VREF/GAIN for AIN1. Therefore, the offset range plus the span range cannot exceed 1.05 VREF/ GAIN for AIN1. If the span is at its minimum (0.8 VREF/ GAIN), the maximum the offset can be is (0.25 VREF/GAIN) for AIN1. For AIN2, both ranges are multiplied by a factor of 4. In the bipolar mode, the system offset calibration range is again restricted by the span range. The span range of the converter in bipolar mode is equidistant around the voltage used for the zero-scale point, thus the offset range plus half the span range cannot exceed (1.05 × V REF/GAIN) for AIN1. If the span is set to 2 ×VREF/GAIN, the offset span cannot move more than ±(0.05 × V REF/GAIN) before the endpoints of the transfer func- tion exceed the input overrange limits ±(1.05 × V REF/GAIN) for AIN1. If the span range is set to the minimum ±(0.4 × VREF/ GAIN), the maximum allowable offset range is ±(0.65 × V REF/ GAIN) for AIN1. Once again, for AIN2, both ranges are multiplied by a factor of 4. POWER-UP AND CALIBRATION On power-up, the AD7712 performs an internal reset, which sets the contents of the control register to a known state. How- ever, to ensure correct calibration for the device, a calibration routine should be performed after power-up. The power dissipation and temperature drift of the AD7712 are low and no warm-up time is required before the initial calibra- tion is performed. However, if an external reference is being used, this reference must have stabilized before calibration is initiated. Drift Considerations The AD7712 uses chopper stabilization techniques to minimize input offset drift. Charge injection in the analog switches and dc leakage currents at the sampling node are the primary sources of offset voltage drift in the converter. The dc input leakage cur- rent is essentially independent of the selected gain. Gain drift within the converter depends primarily upon the temperature tracking of the internal capacitors. It is not affected by leakage currents. Measurement errors due to offset drift or gain drift can be elimi- nated at any time by recalibrating the converter or by operating the part in the background calibration mode. Using the system calibration mode can also minimize offset and gain errors in the signal conditioning circuitry. Integral and differential linearity errors are not significantly affected by temperature changes. POWER SUPPLIES AND GROUNDING Since the analog inputs and reference input are differential, most of the voltages in the analog modulator are common-mode voltages. VBIAS provides the return path for most of the analog currents flowing in the analog modulator. As a result, the VBIAS input should be driven from a low impedance to minimize errors due to charging/discharging impedances on this line. When the internal reference is used as the reference source for the part, AGND is the ground return for this reference voltage. The analog and digital supplies to the AD7712 are independent and separately pinned out to minimize coupling between the analog and digital sections of the device. The digital filter will provide rejection of broadband noise on the power supplies, except at integer multiples of the modulator sampling frequency. The digital supply (DVDD) must not exceed the analog positive supply (AVDD) by more than 0.3 V in normal operation. If sepa- rate analog and digital supplies are used, the decoupling scheme shown in Figure 10 is recommended. In systems where AVDD = 5 V and DVDD = 5 V, it is recommended that AVDD and DVDD are driven from the same 5 V supply, although each supply should be decoupled separately as shown in Figure 10. It is preferable that the common supply is the system’s analog 5 V supply. It is also important that power is applied to the AD7712 before signals at REF IN, AIN, or the logic input pins in order to avoid excessive current. If separate supplies are used for the AD7712 and the system digital circuitry, then the AD7712 should be powered up first. If it is not possible to guarantee this, then current limiting resistors should be placed in series with the logic inputs. AD7712 0.1 F 0.1 F 10 F ANALOG SUPPLY DIGITAL 5V SUPPLY AVDD DVDD Figure 10. Recommended Decoupling Scheme |
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