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PXAG49KBBD Datasheet(PDF) 19 Page - NXP Semiconductors

Part No. PXAG49KBBD
Description  XA 16-bit microcontroller family
Download  42 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

PXAG49KBBD Datasheet(HTML) 19 Page - NXP Semiconductors

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Philips Semiconductors
Preliminary data
XA-G49
XA 16-bit microcontroller family
64K Flash/2K RAM, watchdog, 2 UARTs
2001 Jun 27
19
XA-G49 TIMER/COUNTERS
The XA has two standard 16-bit enhanced Timer/Counters: Timer 0
and Timer 1. Additionally, it has a third 16-bit Up/Down
timer/counter, T2. A central timing generator in the XA core provides
the time-base for all XA Timers and Counters. The timer/event
counters can perform the following functions:
– Measure time intervals and pulse duration
– Count external events
– Generate interrupt requests
– Generate PWM or timed output waveforms
All of the timer/counters (Timer 0, Timer 1 and Timer 2) can be
independently programmed to operate either as timers or event
counters via the C/T bit in the TnCON register. All timers count up
unless otherwise stated. These timers may be dynamically read
during program execution.
The base clock rate of all of the timers is user programmable. This
applies to timers T0, T1, and T2 when running in timer mode (as
opposed to counter mode), and the watchdog timer. The clock
driving the timers is called TCLK and is determined by the setting of
two bits (PT1, PT0) in the System Configuration Register (SCR).
The frequency of TCLK may be selected to be the oscillator input
divided by 4 (Osc/4), the oscillator input divided by 16 (Osc/16), or
the oscillator input divided by 64 (Osc/64). This gives a range of
possibilities for the XA timer functions, including baud rate
generation, Timer 2 capture. Note that this single rate setting applies
to all of the timers.
When timers T0, T1, or T2 are used in the counter mode, the
register will increment whenever a falling edge (high to low
transition) is detected on the external input pin corresponding to the
timer clock. These inputs are sampled once every 2 oscillator
cycles, so it can take as many as 4 oscillator cycles to detect a
transition. Thus the maximum count rate that can be supported is
Osc/4. The duty cycle of the timer clock inputs is not important, but
any high or low state on the timer clock input pins must be present
for 2 oscillator cycles before it is guaranteed to be “seen” by the
timer logic.
Timer 0 and Timer 1
The “Timer” or “Counter” function is selected by control bits C/T in
the special function register TMOD. These two Timer/Counters have
four operating modes, which are selected by bit-pairs (M1, M0) in
the TMOD register. Timer modes 1, 2, and 3 in XA are kept identical
to the 80C51 timer modes for code compatibility. Only the mode 0 is
replaced in the XA by a more powerful 16-bit auto-reload mode. This
will give the XA timers a much larger range when used as time
bases.
The recommended M1, M0 settings for the different modes are
shown in Figure 6.
——
PT1
PT0
CM
PZ
PT1
PT0
OPERATING
Prescaler selection.
0
0
Osc/4
0
1
Osc/16
1
0
Osc/64
1
1
Reserved
CM
Compatibility Mode allows the XA to execute most translated 80C51 code on the XA. The
XA register file must copy the 80C51 mapping to data memory and mimic the 80C51 indirect
addressing scheme.
PZ
Page Zero mode forces all program and data addresses to 16-bits only. This saves stack space
and speeds up execution but limits memory access to 64k.
SU00589
SCR
Address:440
Not Bit Addressable
Reset Value: 00H
LSB
MSB
Figure 5. System Configuration Register (SCR)
GATE
C/T
M1
M0
GATE
C/T
M1
M0
LSB
MSB
GATE
Gating control when set. Timer/Counter “n” is enabled only while “INTn” pin is high and
“TRn” control bit is set. When cleared Timer “n” is enabled whenever “TRn” control bit is set.
C/T
Timer or Counter Selector cleared for Timer operation (input from internal system clock.)
Set for Counter operation (input from “Tn” input pin).
M1
M0
OPERATING
0
0
16-bit auto-reload timer/counter
0
1
16-bit non-auto-reload timer/counter
1
0
8-bit auto-reload timer/counter
1
1
Dual 8-bit timer mode (timer 0 only)
SU00605
TIMER 1
TIMER 0
TMOD
Address:45C
Not Bit Addressable
Reset Value: 00H
Figure 6. Timer/Counter Mode Control (TMOD) Register


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