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74HC373 Datasheet(PDF) 13 Page - NXP Semiconductors |
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74HC373 Datasheet(HTML) 13 Page - NXP Semiconductors |
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13 / 26 page  74HC_HCT373 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 13 December 2011 13 of 26 NXP Semiconductors 74HC373; 74HCT373 Octal D-type transparent latch; 3-state [1] tpd is the same as tPLH and tPHL. [2] ten is the same as tPZH and tPZL. [3] tdis is the same as tPLZ and tPHZ. [4] tt is the same as tTHL and tTLH. [5] CPD is used to determine the dynamic power dissipation (PD in W). PD =CPD VCC2 fi N+ (CL VCC2 fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (C L VCC 2 f o) = sum of outputs. th hold time Dn to LE; see Figure 11 VCC = 2.0 V 5 - - ns VCC = 4.5 V 5 - - ns VCC = 6.0 V 5 - - ns Table 8. Dynamic characteristics 74HC373 …continued Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12. Symbol Parameter Conditions Min Typ Max Unit Table 9. Dynamic characteristics 74HCT373 Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12. Symbol Parameter Conditions Min Typ Max Unit Tamb =25 C tpd propagation delay Dn to Qn; see Figure 8 [1] VCC = 4.5 V - 17 30 ns VCC =5V; CL =15 pF - 14 - ns LE to Qn; see Figure 9 VCC = 4.5 V - 16 32 ns VCC =5V; CL =15 pF - 13 - ns ten enable time OE to Qn; see Figure 10 [2] VCC = 4.5 V - 19 32 ns tdis disable time OE to Qn; see Figure 10 [3] VCC = 4.5 V - 18 30 ns tt transition time Qn; see Figure 8 and Figure 9 [4] VCC = 4.5 V - 5 12 ns tW pulse width LE HIGH; see Figure 9 VCC = 4.5 V 16 4 - ns tsu set-up time Dn to LE; see Figure 11 VCC = 4.5 V 12 6 - ns th hold time Dn to LE; see Figure 11 VCC = 4.5 V 4 1- ns CPD power dissipation capacitance per latch; VI =GND to (VCC 1.5 V) [5] -41 -pF |
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