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LY62W10248ML-55SL Datasheet(PDF) 6 Page - Lyontek Inc. |
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LY62W10248ML-55SL Datasheet(HTML) 6 Page - Lyontek Inc. |
6 / 13 page ![]() LY62W10248 Rev. 1.7 1024K X 8 BIT LOW POWER CMOS SRAM Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 5 AC ELECTRICAL CHARACTERISTICS (1) READ CYCLE PARAMETER SYM. LY62W10248-55 LY62W10248-70 UNIT MIN. MAX. MIN. MAX. Read Cycle Time tRC 55 - 70 - ns Address Access Time tAA - 55 - 70 ns Chip Enable Access Time tACE - 55 - 70 ns Output Enable Access Time tOE - 30 - 35 ns Chip Enable to Output in Low-Z tCLZ* 10 - 10 - ns Output Enable to Output in Low-Z tOLZ* 5 - 5 - ns Chip Disable to Output in High-Z tCHZ* - 20 - 25 ns Output Disable to Output in High-Z tOHZ* - 20 - 25 ns Output Hold from Address Change tOH 10 - 10 - ns (2) WRITE CYCLE PARAMETER SYM. LY62W10248-55 LY62W10248-70 UNIT MIN. MAX. MIN. MAX. Write Cycle Time tWC 55 - 70 - ns Address Valid to End of Write tAW 50 - 60 - ns Chip Enable to End of Write tCW 50 - 60 - ns Address Set-up Time tAS 0 - 0 - ns Write Pulse Width tWP 45 - 55 - ns Write Recovery Time tWR 0 - 0 - ns Data to Write Time Overlap tDW 25 - 30 - ns Data Hold from End of Write Time tDH 0 - 0 - ns Output Active from End of Write tOW* 5 - 5 - ns Write to Output in High-Z tWHZ* - 20 - 25 ns *These parameters are guaranteed by device characterization, but not production tested. |
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