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DRV8313PWP Datasheet(PDF) 8 Page - Texas Instruments

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Part # DRV8313PWP
Description  DRV8313 TRIPLE HALF-H-BRIDGE DRIVER IC
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

DRV8313PWP Datasheet(HTML) 8 Page - Texas Instruments

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PGND1
PGND2
PGND3
COMPP
COMPO
COMPN
Current Limit
R
SENSE
V
REF
V3P3OUT
B0482-01
DRV8313
SLVSBA5A – OCTOBER 2012 – REVISED NOVEMBER 2012
www.ti.com
Comparator
The DRV8313 includes an uncommitted comparator, which can find use as a current-limit comparator or for other
purposes.
The following diagram shows connections to use the comparator to sense current for implementing a current
limit. Current from all three low-side FETs is sensed using a single low-side sense resistor. The voltage across
the sense resistor is compared with a reference, and when the sensed voltage exceeds the reference, a current-
limit condition is signaled to the controller. The V3P3OUT internal voltage regulator can be used to set the
reference voltage of the comparator.
Figure 3. DRV8313 Comparator
nRESET and nSLEEP Operation
The nRESET pin, when driven active-low, resets any faults. It also disables the output drivers while it is active.
The device ignores all inputs while nRESET is active. Note that there is an internal power-up-reset circuit, so that
driving nRESET at power up is not required.
Driving nSLEEP low puts the device into a low-power sleep state. Entering this state disables the output drivers,
stops the gate-drive charge pump, resets all internal logic (including faults), and stops all internal clocks. In this
state, the device ignores all inputs until nSLEEP returns inactive-high. When returning from sleep mode, some
time (approximately 1 ms) must pass before the motor driver becomes fully operational. Note that the V3P3
regulator remains operational in sleep mode.
Protection Circuits
The DRV8313 has full protection against undervoltage, overcurrent, and overtemperature events.
OVERCURRENT PROTECTION (OCP)
An analog current-limit circuit on each FET limits the current through the FET by removing the gate drive. If
this analog current limit persists for longer than the OCP deglitch time, the device disables the channel
experiencing the overcurrent and drives the nFAULT pin low. The driver remains off until either assertion of
nRESET or the cycling of VM power.
Overcurrent conditions on both high- and low-side devices, that is, a short to ground, supply, or across the
motor winding, all result in an overcurrent shutdown.
THERMAL SHUTDOWN (TSD)
If the die temperature exceeds safe limits, the device disables all outputs and drives the nFAULT pin low.
Once the die temperature has fallen to a safe level, operation automatically resumes.
8
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Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: DRV8313


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