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LY61L102416AGL-12I Datasheet(PDF) 8 Page - Lyontek Inc. |
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LY61L102416AGL-12I Datasheet(HTML) 8 Page - Lyontek Inc. |
8 / 13 page LY61L102416A Rev. 1.4 1024K X 16 BIT HIGH SPEED CMOS SRAM Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, lndustry E . Rd. 9, Science-Based Industrial Park, Hsinchu 300, Taiwan TEL: 886-3-6668838 FAX: 886-3-6668836 7 ® WRITE CYCLE 3 (LB#,UB# Controlled) (1,2,5,6) Dout Din Data Valid tDW tDH (4) High-Z tWHZ WE# LB#,UB# tCW CE# Address tWR tAS tAW tWC tWP tBW Notes : 1.WE#,CE#, LB#, UB# must be high during all address transitions. 2.A write occurs during the overlap of a low CE#, low WE#, LB# or UB# = low. 3.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be placed on the bus. 4.During this period, I/O pins are in the output state, and input signals must not be applied. 5.If the CE#, LB#, UB# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state. 6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. |
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