LY61L51216A

Rev. 1.3

512K X 16 BIT HIGH SPEED CMOS SRAM

5F, No. 2, lndustry E . Rd. 9, Science-Based Industrial Park, Hsinchu 300, Taiwan

TEL: 886-3-6668838

FAX: 886-3-6668836

7

®

Dout

Din

Data Valid

(4)

High-Z

WE#

LB#,UB#

CE#

Address

Notes :

1.WE#,CE#, LB#, UB# must be high during all address transitions.

2.A write occurs during the overlap of a low CE#, low WE#, LB# or UB# = low.

on the bus.

4.During this period, I/O pins are in the output state, and input signals must not be applied.

5.If the CE#, LB#, UB# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state.

DATA RETENTION CHARACTERISTICS

PARAMETER

SYMBOL

TEST CONDITION

MIN.

TYP.

MAX.

UNIT

CE#

V

1.5

-

3.6

V

Data Retention Current

CE#

V

Other pin is at 0.2V or

Vcc-0.2V

-

-

3

25

mA

Chip Disable to Data

Retention Time

See Data Retention

Waveforms (below)

0

-

-

ns

Recovery Time

-

-

ns

DATA RETENTION WAVEFORM

Vcc

CE#

CE#

V

≧

cc-0.2V

Vcc(min.)

Vcc(min.)