LY61L102416A

Rev. 1.4

1024K X 16 BIT HIGH SPEED CMOS SRAM

5F, No. 2, lndustry E . Rd. 9, Science-Based Industrial Park, Hsinchu 300, Taiwan

TEL: 886-3-6668838

FAX: 886-3-6668836

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REVISION HISTORY

Revision

Description

Issue Date

Rev. 1.0

Initial Issued

Jan.09. 2012

Rev. 1.1

Add 48 pin BGA package type.

Mar.12. 2012

Rev. 1.2

CONDITION of Average Operating Power supply Current

Icc1 on page3

2.Revised ORDERING INFORMATION Page11

July.19. 2012

Rev. 1.3

1.Revise “TEST CONDITION” for VOH, VOL on page 3

revised as 8mA

2. Revise VIH(max) & VIL(min) note on page 3

VIH(max) = VCC + 2.0V for pulse width less than 6ns.

VIL(min) = VSS - 2.0V for pulse width less than 6ns.

June. 04. 2013

Rev.1.4

Revised the address pin sequence of pin configuration of 48 pin

TSOP-I on page 2 in order to be compatible with industry convention.

(No function specifications and applications have been changed and all

the characteristics are kept all the same as Rev 1.3 )

Oct. 30. 2013