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74HCT138BQ-Q100 Datasheet(PDF) 3 Page - NXP Semiconductors |
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74HCT138BQ-Q100 Datasheet(HTML) 3 Page - NXP Semiconductors |
3 / 18 page 74HC_HCT138_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 1 — 16 July 2012 3 of 18 NXP Semiconductors 74HC138-Q100; 74HCT138-Q100 3-to-8 line decoder/demultiplexer; inverting 5. Pinning information 5.1 Pinning Fig 3. Logic diagram 001aae059 Y6 Y7 E1 E2 E3 A0 A1 A2 Y4 Y5 Y2 Y3 Y0 Y1 (1) The die substrate is attached to this pad using conductive die attach material. It cannot be used as supply pin or input. Fig 4. Pin configuration SO16 and TSSOP16 Fig 5. Pin configuration DHVQFN16 74HC138/Q100 74HCT138/Q100 A0 VCC A1 Y0 A2 Y1 E1 Y2 E2 Y3 E3 Y4 Y7 Y5 GND Y6 aaa-003153 1 2 3 4 5 6 7 8 10 9 12 11 14 13 16 15 aaa-003154 74HC138/Q100 74HCT138/Q100 Y7 Y5 E3 Y4 E2 Y3 E1 Y2 A2 Y1 A1 Y0 Transparent top view 7 10 6 11 5 12 4 13 3 14 2 15 terminal 1 index area GND(1) |
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