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74HCT273N Datasheet(PDF) 9 Page - NXP Semiconductors |
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74HCT273N Datasheet(HTML) 9 Page - NXP Semiconductors |
9 / 21 page 74HC_HCT273 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 4 — 10 June 2013 9 of 21 NXP Semiconductors 74HC273; 74HCT273 Octal D-type flip-flop with reset; positive-edge trigger [1] tpd is the same as tPHL and tPLH. [2] tt is the same as tTHL and tTLH. [3] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD VCC2 fi + (CL VCC2 fo) where: fi = input frequency in MHz; fo = output frequency in MHz; (C L VCC 2 f o) = sum of outputs; CL = output load capacitance in pF; VCC = supply voltage in V. 74HCT273 tpd propagation delay CP to Qn; see Figure 7 [1] VCC = 4.5 V - 16 30 - 38 - 45 ns VCC = 5.0 V; CL =15pF - 15 - - - - - ns tPHL HIGH to LOW propagation delay MR to Qn; see Figure 8 VCC = 4.5 V - 23 34 - 43 - 51 ns VCC = 5.0 V; CL =15pF - 20 - - - - - ns tt transition time Qn output; see Figure 7 [2] VCC = 4.5 V - 7 15 - 19 - 22 ns tW pulse width CP input; see Figure 7 VCC = 4.5 V 16 9 - 20 - 24 - ns MR input LOW; see Figure 8 VCC = 4.5 V 16 8 - 20 - 24 - ns trec recovery time MR to CP; see Figure 8 VCC = 4.5 V 10 2 - 13 - 15 - ns tsu set-up time Dn to CP; see Figure 9 VCC = 4.5 V 12 5 - 15 - 18 - ns th hold time Dn to CP; see Figure 9 VCC = 4.5 V 3 4- 3 - 3 - ns fmax maximum frequency CP input; see Figure 7 VCC = 4.5 V 30 56 - 24 - 20 - MHz VCC = 5.0 V; CL =15pF - 36 - - - - - MHz CPD power dissipation capacitance per package; VI =GND to VCC 1.5 V [3] -23- - - - - pF Table 7. Dynamic characteristics …continued GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 10 Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max |
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