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LY61L256RL-15LLT Datasheet(PDF) 5 Page - Lyontek Inc. |
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LY61L256RL-15LLT Datasheet(HTML) 5 Page - Lyontek Inc. |
5 / 12 page LY61L256 Rev. 1.4 32K X 8 BIT HIGH SPEED CMOS SRAM Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 4 ® Notes: 1. VIH(max) = VCC + 3.0V for pulse width less than 10ns. 2. VIL(min) = VSS - 3.0V for pulse width less than 10ns. 3. Over/Undershoot specifications are characterized, not 100% tested. 4. Typical values are included for reference only and are not guaranteed or tested. Typical valued are measured at VCC = VCC(TYP.) and TA = 25℃ CAPACITANCE (TA = 25 , f ℃ = 1.0MHz) PARAMETER SYMBOL MIN. MAX UNIT Input Capacitance CIN - 6 pF Input/Output Capacitance CI/O - 8 pF Note : These parameters are guaranteed by device characterization, but not production tested. AC TEST CONDITIONS Input Pulse Levels 0.2V to VCC -0.2V Input Rise and Fall Times 3ns Input and Output Timing Reference Levels 1.5V Output Load CL = 30pF + 1TTL, IOH/IOL = -4mA/8mA AC ELECTRICAL CHARACTERISTICS (1) READ CYCLE PARAMETER SYM. LY61L256-10 LY61L256-12 LY61L256-15 UNIT MIN. MAX. MIN. MAX. MIN. MAX. Read Cycle Time tRC 10 - 12 - 15 - ns Address Access Time tAA - 10 - 12 - 15 ns Chip Enable Access Time tACE - 10 - 12 - 15 ns Output Enable Access Time tOE - 5 - 6 - 7 ns Chip Enable to Output in Low-Z tCLZ* 2 - 3 - 4 - ns Output Enable to Output in Low-Z tOLZ* 0 - 0 - 0 - ns Chip Disable to Output in High-Z tCHZ* - 5- 6- 7 ns Output Disable to Output in High-Z tOHZ* - 5- 6- 7 ns Output Hold from Address Change tOH 1 - 3 - 3 - ns (2) WRITE CYCLE PARAMETER SYM. LY61L256-10 LY61L256-12 LY61L256-15 UNIT MIN. MAX. MIN. MAX. MIN. MAX. Write Cycle Time tWC 10 - 12 - 15 - ns Address Valid to End of Write tAW 8 - 10 - 12 - ns Chip Enable to End of Write tCW 8 - 10 - 12 - ns Address Set-up Time tAS 0 - 0 - 0 - ns Write Pulse Width tWP 8 - 9 - 10 - ns Write Recovery Time tWR 0 - 0 - 0 - ns Data to Write Time Overlap tDW 6 - 7 - 8 - ns Data Hold from End of Write Time tDH 0 - 0 - 0 - ns Output Active from End of Write tOW* 2 - 3 - 4 - ns Write to Output in High-Z tWHZ* - 6-7- 8 ns *These parameters are guaranteed by device characterization, but not production tested. |
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