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DS90LV048ATMTC Datasheet(PDF) 8 Page - Texas Instruments

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Part # DS90LV048ATMTC
Description  DS90LV048A 3V LVDS Quad CMOS Differential Line Receiver
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

DS90LV048ATMTC Datasheet(HTML) 8 Page - Texas Instruments

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DS90LV048A
SNLS045B – JULY 1999 – REVISED APRIL 2013
www.ti.com
Match electrical lengths between traces to reduce skew. Skew between the signals of a pair means a phase
difference between signals which destroys the magnetic field cancellation benefits of differential signals and EMI
will result. (Note the velocity of propagation, v = c/Er where c (the speed of light) = 0.2997mm/ps or 0.0118
in/ps). Do not rely solely on the autoroute function for differential traces. Carefully review dimensions to match
differential impedance and provide isolation for the differential lines. Minimize the number or vias and other
discontinuities on the line.
Avoid 90° turns (these cause impedance discontinuities). Use arcs or 45° bevels.
Within a pair of traces, the distance between the two traces should be minimized to maintain common-mode
rejection of the receivers. On the printed circuit board, this distance should remain constant to avoid
discontinuities in differential impedance. Minor violations at connection points are allowable.
Termination
Use a termination resistor which best matches the differential impedance or your transmission line. The resistor
should be between 90
Ω and 130Ω. Remember that the current mode outputs need the termination resistor to
generate the differential voltage. LVDS will not work without resistor termination. Typically, connecting a single
resistor across the pair at the receiver end will suffice.
Surface mount 1% to 2% resistors are best. PCB stubs, component lead, and the distance from the termination
to the receiver inputs should be minimized. The distance between the termination resistor and the receiver
should be < 10mm (12mm MAX)
Probing LVDS Transmission Lines
Always use high impedance (> 100k
Ω), low capacitance (< 2 pF) scope probes with a wide bandwidth (1 GHz)
scope. Improper probing will give deceiving results.
Cables and Connectors, General Comments
When choosing cable and connectors for LVDS it is important to remember:
Use controlled impedance media. The cables and connectors you use should have a matched differential
impedance of about 100
Ω. They should not introduce major impedance discontinuities.
Balanced cables (e.g. twisted pair) are usually better than unbalanced cables (ribbon cable, simple coax.) for
noise reduction and signal quality. Balanced cables tend to generate less EMI due to field canceling effects and
also tend to pick up electromagnetic radiation a common-mode (not differential mode) noise which is rejected by
the receiver.
For cable distances < 0.5M, most cables can be made to work effectively. For distances 0.5M
≤ d ≤ 10M, CAT 3
(category 3) twisted pair cable works well, is readily available and relatively inexpensive.
Threshold
The LVDS Standard (ANSI/TIA/EIA-644) specifies a maximum threshold of ±100mV for the LVDS receiver. The
DS90LV048A supports an enhanced threshold region of
−100mV to 0V. This is useful for fail-safe biasing. The
threshold region is shown in the Voltage Transfer Curve (VTC) in Figure 6. The typical DS90LV048A LVDS
receiver switches at about
−35mV. Note that with VID = 0V, the output will be in a HIGH state. With an external
fail-safe bias of +25mV applied, the typical differential noise margin is now the difference from the switch point to
the bias point. In the example below, this would be 60mV of Differential Noise Margin (+25mV
− (−35mV)). With
the enhanced threshold region of
−100mV to 0V, this small external fail-safe biasing of +25mV (with respect to
0V) gives a DNM of a comfortable 60mV. With the standard threshold region of ±100mV, the external fail-safe
biasing would need to be +25mV with respect to +100mV or +125mV, giving a DNM of 160mV which is stronger
fail-safe biasing than is necessary for the DS90LV048A. If more DNM is required, then a stronger fail-safe bias
point can be set by changing resistor values.
8
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