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ADN2892ACPZ-500RL7 Datasheet(PDF) 12 Page - Analog Devices

Part No. ADN2892ACPZ-500RL7
Description  3.3 V, 4.25 Gbps, Limiting Amplifier
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ADN2892ACPZ-500RL7 Datasheet(HTML) 12 Page - Analog Devices

 
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ADN2892
Data Sheet
Rev. A | Page 12 of 16
PCB Layout
Figure 19 shows the recommended PCB layout. The 50 Ω
transmission lines are the traces that bring the high frequency
input and output signals (PIN, NIN, OUTP, and OUTN) from a
terminated source to a terminated load with minimum
reflection. To avoid a signal skew between the differential
traces, each differential PIN/NIN and OUTP/OUTN pair
should have matched trace lengths from a differential source to
a differential load. C1, C2, C3, and C4 are ac coupling
capacitors in series with the high speed, signal input/output
paths. To minimize the possible mismatch, the ac coupling
capacitor pads should be the same width as the 50 Ω
transmission line trace width. To reduce supply noise, a 1 nF
decoupling capacitor should be placed as close as possible to the
VCC pins on the same layer and not through vias. A 0.1 μF
decoupling capacitor can be placed on the bottom of the PCB
directly underneath the 1 nF capacitor. All high speed, CML
outputs have internal 50 Ω resistor termination between the
output pin and VCC. The high speed inputs, PIN and NIN, also
have the internal 50 Ω termination to an internal reference
voltage.
As with any high speed, mixed-signal design, keep all high
speed digital traces away from sensitive analog nodes.
Soldering Guidelines for the LFCSP
The lands on the 16-lead LFCSP are rectangular. The PCB pad
for these should be 0.1 mm longer than the package land length
and 0.05 mm wider than the package land width. The land
should be centered on the pad. This ensures that the solder joint
size is maximized. The bottom of the LFCSP has a central
exposed pad. The pad on the printed circuit board should be at
least as large as the exposed pad. Users must connect the
exposed pad to VEE using filled vias so that solder does not
leak through the vias during reflow. This ensures a solid
connection from the exposed pad to VEE.
PAD COATING AND PB-FREE SOLDERING
Table 5.
Pad Coating
Matt-Tin
Pb-Free Reflow Portfolio
J-STD-20B
1
FILLED VIAS TO
GND
EXPOSED PAD
PIN
NIN
VIA TO C12, R2
ON BOTTOM
VIAS TO BOTTOM
DOUBLE-VIA TO GND
TO REDUCE INDUCTANCE
C3
C8
C4
C1
C2
OUTP
DOUBLE-VIAS TO REDUCE
INDUCTANCE TO SUPPLY
AND GND
R1, C9, C10 ON BOTTOM
TO ROSA
PLACE C7 ON
BOTTOM OF BOARD
UNDERNEATH C8
OUTN
PLACE C5 ON
BOTTOM OF BOARD
UNDERNEATH C6
4mm
TRANSMISSION LINES SAME
WIDTH AS AC COUPLING
CAPS TO REDUCE REFLECTIONS
GND
AVCC
DVCC GND
C6
Figure 19. Recommended ADN2892 PCB Layout (Top View)


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