115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

6277

8-BIT SERIAL-INPUT,

CONSTANT-CURRENT

LATCHED LED DRIVER

6

TIMING REQUIREMENTS and SPECIFICATIONS

A. Data Active Time Before Clock Pulse

B. Data Active Time After Clock Pulse

D. Time Between Clock Activation

NOTE – Timing is representative of a 10 MHz clock.

Significantly higher speeds are attainable.

Information present at any register is transferred to the

respective latch when the LATCH ENABLE is high (serial-to-

parallel conversion). The latches will continue to accept new

data as long as the LATCH ENABLE is held high. Applica-

tions where the latches are bypassed (LATCH ENABLE tied

high) will require that the OUTPUT ENABLE input be high

during serial data entry.

When the OUTPUT ENABLE input is high, the output

source drivers are disabled (OFF). The information stored in the

latches is not affected by the OUTPUT ENABLE input. With

the OUTPUT ENABLE input low, the outputs are controlled by

the state of their respective latches.

OUTPUT

ENABLE

Dwg. WP-030-1

DATA

10%

50%

dis(BQ)

t

F

en(BQ)

t

HIGH = ALL OUTPUTS DISABLED (BLANKED)

f

t

r

t

90%

CLOCK

SERIAL

DATA IN

LATCH

ENABLE

OUTPUT

ENABLE

Dwg. WP-029-3

50%

SERIAL

DATA OUT.

1

DATA

DATA

50%

50%

50%

C

A

B

D

E

LOW = ALL OUTPUTS ENABLED

p

t

DATA

50%

p

t

LOW = OUTPUT ON

HIGH = OUTPUT OFF

SERIAL

DATA

50%

p

t