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TPS65311-Q1 Datasheet(PDF) 10 Page - Texas Instruments

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Part # TPS65311-Q1
Description  High-Voltage Power-Management IC for Automotive Safety Applications
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TPS65311-Q1 Datasheet(HTML) 10 Page - Texas Instruments

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TPS65311-Q1
SLVSCA6A – OCTOBER 2013 – REVISED OCTOBER 2013
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
VIN = VINPROT 4.8 V to 40 V, VSUPx = 3 V to 5.5 V, EXTSUP = 0 V, TJ(max) = 125°C, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOLTAGE MONITORS BUCK1/2/3, VIO, LDO, BOOSTER
VMONTH_L
Voltage monitor reference
REF = 0.8 V – falling edge
90
92
94
%
VMONTH_H
Voltage monitor reference
REF = 0.8 V – rising edge
106
108
110
%
VMON_HY
Voltage monitor hysteresis
2
%
Undervoltage monitoring at VIO –
VVIOMON_TH
3
3.13
V
falling edge
VVIOMON_HY
UV_VIO hysteresis
0.05
V
Blanking time between UV/OV
tVMON_BLK
UV/OV: BUCK1/2/3 UV: VIO
10
20
µs
condition to RESN low
Blanking time between undervoltage
BUCK1/2/3
→ ERROR mode LDO or BOOST → SPI
tVMONTHL_BLK
condition to ERROR mode transition
1
ms
bit set or turn off
or corresponding SPI bit
Blanking time between undervoltage
tVMONTHL_BLK1
VIO only
10
20
µs
condition to ERROR mode transition
Blanking time between overvoltage
BUCK1/2/3
→ ERROR mode VIO has no OV
tVMONTHH_BLK1
10
20
µs
condition to ERROR mode transition
protection
Blanking time LDO and BOOST
LDO or BOOST (ACTIVE mode)
→ SPI bit set or turn
overvoltage condition to
tVMONTHH_BLK2
off LDO (VTCHECK or RAMP mode)
→ ERROR
20
40
µs
corresponding SPI bit or ERROR
mode
mode
GND LOSS
VGLTH-low
GND loss threshold low
GND to PGNDx
–0.31
–0.25
–0.19
V
VGLTH-high
GND loss threshold high
GND to PGNDx
0.19
0.25
0.31
V
Blanking time between GND loss
tGL-BLK
condition and transition to ERROR
10
20
µs
state
POWER-UP SEQUENCING
tSTART1
Soft start time of BOOST
From start till exceeding VMONTH_L + VMON_HY Level
0.7
2.7
ms
Soft start time of BUCK1/2/3 and
tSTART2
From start till exceeding VMONTH_L + VMON_HY Level
0.5
2
ms
LDO
tSTART
Startup DVDD regulator
From start till exceeding VMONTH_L + VMON_HY Level
3
ms
Sequencing time from start of
tSEQ2
Internal SSDONE_BUCK1 signal
3
ms
BUCK1 to BUCK2 and BOOST
Startup time from entering
tWAKE-RES
GPFET = IRFR6215
14
ms
TESTSTART to RESN high
Sequencing time from start of
tSEQ1
Internal SSDONE_BOOST signal
1
4
ms
BOOST to BUCK3
INTERNAL VOLTAGE REGULATORS — TJ(max) = 125°C
IVREG = 0 mA to 50 mA, VINPROT = 6.3 V to 40 V and
VREG
Internal regulated supply
5.5
5.8
6.1
V
EXTSUP = 6.3 V to 12 V
IVREG = 0 mA to 50 mA and EXTSUP ramping positive,
VEXTSUP-TH
Switch over voltage
4.4
4.6
4.8
V
ACTIVE mode
VEXTSUP-HY
Switch over hysteresis
100
200
300
mV
IVREG = 50 mA,
VREGDROP
Drop out voltage on VREG
EXTSUP = 5 V / VINPROT = 5 V and
200
mV
EXTSUP = 0 V / VINPROT = 4 V
IREG_CL
EXTSUP = 0 V, VREG = 0 V
–250
–50
mA
Current limit on VREG
IREG_EXTSUP_CL
EXTSUP
≥ 4.8 V, VREG = 0 V
–250
–50
mA
CVREG
Capacitive load
1.2
2.2
3.3
µF
VREG rising
3.8
4
4.2
V
VREG-OK
VREG undervoltage threshold
Hysteresis
350
420
490
mV
VDVDD
Internal regulated low voltage supply
3.15
3.3
3.45
V
VDVDD UV
DVDD undervoltage threshold
DVDD falling
2.1
V
VDVDD OV
DVDD overvoltage threshold
DVDD rising
3.8
V
Blanking time from DVDD
tDVDD OV
overvoltage condition to shutdown
10
20
µs
mode transition
10
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