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5832 Datasheet(PDF) 4 Page - Allegro MicroSystems

Part No. 5832
Description  BiMOS II 32-BIT SERIAL-INPUT, LATCHED DRIVERS
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Maker  ALLEGRO [Allegro MicroSystems]
Homepage  http://www.allegromicro.com
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5832 Datasheet(HTML) 4 Page - Allegro MicroSystems

   
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5832
BiMOS II 32-BIT
SERIAL-INPUT,
LATCHED DRIVERS
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Serial Data present at the input is trans-
ferred to the shift register on the logic “0” to
logic “1” transition of the CLOCK input pulse.
On succeeding CLOCK pulses, the registers
shift data information towards the SERIAL
DATA OUTPUT. The SERIAL DATA must
appear at the input prior to the rising edge of
the CLOCK input waveform.
Information present at any register is
transferred to its respective latch when the
STROBE is high (serial-to-parallel conver-
sion). The latches will continue to accept
new data as long as the STROBE is held
high. Applications where the latches are
bypassed (STROBE tied high) will require
that the OUTPUT ENABLE input be low
during serial data entry.
When the OUTPUT ENABLE input is low,
all of the output buffers are disabled (OFF)
without affecting the information stored in the
latches or shift register. With the OUTPUT
ENABLE input high, the outputs are con-
trolled by the state of the latches.
E
F
CLOCK
DATA IN
STROBE
N
A
D
B
C
G
OUTPUT
ENABLE
OUT
Dwg. No. A-12,276A
TRUTH TABLE
Serial
Shift Register Contents
Serial
Latch Contents
Output
Output Contents
Data
Clock
Data
Strobe
Enable
Input
Input I1
I2
I3
...
IN-1 IN
Output
Input
I1
I2
I3
...
IN-1 IN
Input
I1 I2 I3 ... IN-1 IN
HH
R1 R2 ...
RN-2 RN-1
RN-1
LL
R1 R2 ...
RN-2 RN-1
RN-1
XR1 R2 R3 ...
RN-1 RN
RN
XXX...
X
X
X
L
R1 R2 R3 ...
RN-1 RN
P1 P2 P3 ...
PN-1 PN
PN
HP1 P2 P3 ...
PN-1 PN
HP1 P2 P3 ... PN-1 PN
X
X
X
...
X
X
L
H
H
H
... H
H
L = Low Logic Level
H = High Logic Level
X = Irrelevant
P = Present State
R = Previous State
TIMING CONDITIONS
(VDD = 5.0 V, Logic Levels are VDD and Ground)
A. Minimum Data Active Time Before Clock Pulse
(Data Set-Up Time) .......................................................................... 75 ns
B. Minimum Data Active Time After Clock Pulse
(Data Hold Time) ............................................................................. 75 ns
C. Minimum Data Pulse Width ................................................................ 150 ns
D. Minimum Clock Pulse Width ............................................................... 150 ns
E. Minimum Time Between Clock Activation and Strobe ....................... 300 ns
F. Minimum Strobe Pulse Width ............................................................. 100 ns
G. Typical Time Between Strobe Activation and
Output Transition ........................................................................... 500 ns


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