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TPS62152-Q1 Datasheet(PDF) 3 Page - Texas Instruments |
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TPS62152-Q1 Datasheet(HTML) 3 Page - Texas Instruments |
3 / 35 page TPS62152-Q1 www.ti.com SLVSC52A – JULY 2013 – REVISED JULY 2013 ELECTRICAL CHARACTERISTICS over free-air temperature range (TA= –40°C to 125°C), typical values at VIN = AVIN = PVIN = 12 V and TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY VIN Input Voltage Range(1) 3 17 V IQ Operating Quiescent Current EN = High, IOUT = 0 mA, device not switching 17 25 µA ISD Shutdown Current(2) EN = Low 1.5 4 µA VUVLO Falling Input Voltage 2.6 2.7 2.8 V Undervoltage Lockout Threshold Hysteresis 200 mV TSD Thermal Shutdown Temperature 160 °C Thermal Shutdown Hysteresis 20 CONTROL (EN, DEF, FSW, SS/TR, PG) High Level Input Threshold Voltage (EN, VH 0.9 V DEF, FSW) VL Low Level Input Threshold Voltage (EN, 0.3 V DEF, FSW) ILKG Input Leakage Current (EN, DEF, FSW) EN = VIN or GND; DEF, FSW = VOUT or GND 0.01 1 µA Rising (%VOUT) 92 95 98 VTH_PG Power Good Threshold Voltage % Falling (%VOUT) 87 90 94 VOL_PG Power Good Output Low IPG = –2 mA 0.07 0.3 V ILKG_PG Input Leakage Current (PG) VPG = 1.8 V 1 400 nA ISS/TR SS/TR Pin Source Current 2.3 2.5 2.7 µA POWER SWITCH VIN ≥ 6 V 90 170 High-Side MOSFET ON-Resistance m Ω VIN = 3 V 120 RDS(ON) VIN ≥ 6 V 40 70 Low-Side MOSFET ON-Resistance m Ω VIN = 3 V 50 ILIMF High-Side MOSFET Forward Current Limit(3) VIN = 12 V, TA= 25°C 1.4 1.7 2.2 A OUTPUT VREF Internal Reference Voltage(4) 0.8 V ILKG_FB Input Leakage Current (FB) TPS62150-Q1, VFB = 0.8 V 1 100 nA Output Voltage Range (TPS62150-Q1) VIN ≥ VOUT 0.9 6 V DEF (Output Voltage Programming) DEF = 0 (GND) VOUT DEF = 1 (VOUT) VOUT + 5% PWM mode operation, VIN ≥ VOUT + 1 V –1.8 1.8 Initial Output Voltage Accuracy(5) % VOUT Power Save Mode operation, COUT = 22 µF –2.3 2.8 Load Regulation(6) VIN = 12 V, VOUT = 3.3 V, PWM mode 0.05 %/A operation Line Regulation(6) 3 V ≤ VIN ≤ 17 V, VOUT = 3.3 V, IOUT = 1 A, 0.02 %/V PWM mode operation (1) The device is still functional down to Under Voltage Lockout (see parameter VUVLO). (2) Current into AVIN + PVIN pin. (3) This is the static current limit. It can be temporarily higher in applications due to internal propagation delay (see Current Limit And Short Circuit Protection section). (4) This is the voltage regulated at the FB pin. (5) This is the accuracy provided by the device itself (line and load regulation effects are not included). For the fixed voltage versions the (internal) resistive divider is included. (6) Line and load regulation depend on external component selection and layout (see Figure 17 and Figure 18). Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: TPS62152-Q1 |
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