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AD5293BRUZ-100 Datasheet(PDF) 20 Page - Analog Devices |
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AD5293BRUZ-100 Datasheet(HTML) 20 Page - Analog Devices |
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20 / 24 page  AD5293 Rev. D | Page 20 of 24 Table 13. Control Register Function Register Name Bit Name Description Control C2 Calibration enable. 0 = resistor performance mode (default). 1 = normal mode. C1 RDAC register write protect. 0 = locks the wiper position through the digital interface (default). 1 = allows update of wiper position through digital interface. RDAC ARCHITECTURE To achieve optimum performance, Analog Devices, Inc., has patented the RDAC segmentation architecture for all the digital potentiometers. In particular, the AD5293 employs a 3-stage segmentation approach, as shown in Figure 46. The AD5293 wiper switch is designed with transmission gate CMOS topology and with the gate voltage derived from VDD. RW SW W RW 10-BIT ADDRESS DECODER A RL RL RM RM B RM RM RL RL Figure 46. Simplified RDAC Circuit PROGRAMMING THE VARIABLE RESISTOR Rheostat Operation—1% Resistor Tolerance The AD5293 operates in rheostat mode when only two terminals are used as a variable resistor. The unused terminal can be left floating or it can be tied to the W terminal, as shown in Figure 47. W A B W A B W A B Figure 47. Rheostat Mode Configuration The nominal resistance between Terminal A and Terminal B, RAB, is available in 20 kΩ, 50 kΩ, and 100 kΩ and has 1024 tap points that are accessed by the wiper terminal. The 10-bit data in the RDAC latch is decoded to select one of the 1024 possible wiper settings. The AD5293 contains an internal ±1% resistor tolerance calibration feature that can be enabled or disabled, enabled by default by programming Bit C2 of the control register (see Table 12 and Table 13). The digitally programmed output resistance between the W terminal and the A terminal, RWA, and the W terminal and B terminal, RWB, is calibrated to give a maximum of ±1% absolute resistance error over both the full supply and temperature ranges. As a result, the general equation for determining the digitally programmed output resistance between the W terminal and B terminal is AB WB R D D R × = 1024 ) ( (1) where: D is the decimal equivalent of the binary code loaded in the 10-bit RDAC register. RAB is the end-to-end resistance. Similar to the mechanical potentiometer, the resistance of the RDAC between the W terminal and the A terminal also produces a digitally controlled complementary resistance, RWA. RWA is also calibrated to give a maximum of 1% absolute resistance error. RWA starts at the maximum resistance value and decreases as the data loaded into the latch increases. The general equation for this operation is AB WA R D D R × − = 1024 1024 ) ( (2) where: D is the decimal equivalent of the binary code loaded in the 10-bit RDAC register. RAB is the end-to-end resistance. In the zero-scale condition, a finite total wiper resistance of 120 Ω is present. Regardless of the setting in which the part is operating, care should be taken to limit the current between the A terminal to B terminal, the W terminal to the A terminal, and the W terminal to the B terminal to the maximum continuous current of ±3 mA or to the pulse current specified in Table 6. Otherwise, degradation, or possible destruction of the internal switch contact, can occur. |
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