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ADC12D1000 Datasheet(PDF) 20 Page - Texas Instruments |
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ADC12D1000 Datasheet(HTML) 20 Page - Texas Instruments |
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20 / 73 page  ADC12D1000, ADC12D1600 SNAS480M – MAY 2010 – REVISED MARCH 2013 www.ti.com AC Electrical Characteristics ADC12D1000 ADC12D1600 Units Symbol Parameter Conditions (Limits) Typ Lim Typ Lim Sampling Clock (CLK) fCLK (max) Maximum Sampling Clock 1.0 1.6 GHz Frequency fCLK (min) Minimum Sampling Clock Non-DES Mode; LFS = 0b 300 300 MHz Frequency Non-DES Mode; LFS = 1b 150 150 MHz DES Mode 500 500 MHz Sampling Clock Duty Cycle fCLK(min) ≤ fCLK ≤ fCLK(max) (1) 20 20 % (min) 50 50 80 80 % (max) tCL Sampling Clock Low Time See(2) 500 200 312.5 125 ps (min) tCH Sampling Clock High Time See(2) 500 200 312.5 125 ps (min) Data Clock (DCLKI, DCLKQ) DCLK Duty Cycle See(2) 45 45 % (min) 50 50 55 55 % (max) tSR Setup Time DCLK_RST± See(1) 45 45 ps tHR Hold Time DCLK_RST± See(1) 45 45 ps tPWR Pulse Width DCLK_RST± See(2) Sampling Clock 5 5 Cycles (min) tSYNC_DLY DCLK Synchronization Delay 90° Mode(2) 4 4 Sampling Clock 0° Mode(2) 5 5 Cycles tLHT Differential Low-to-High Transition 10%-to-90%, CL = 2.5 pF 200 200 ps Time tHLT Differential High-to-Low Transition 10%-to-90%, CL = 2.5 pF 200 200 ps Time tSU Data-to-DCLK Setup Time 90° Mode(2) 870 500 ps tH DCLK-to-Data Hold Time 90° Mode(2) 870 500 ps tOSK DCLK-to-Data Output Skew 50% of DCLK transition to 50% of ±50 ±50 ps (max) Data transition(2) Data Input-to-Output tAD Aperture Delay Sampling CLK+ Rise to 1.15 1.15 ns Acquisition of Data tAJ Aperture Jitter 0.2 0.2 ps (rms) tOD Sampling Clock-to Data Output 50% of Sampling Clock transition 3.2 3.2 ns Delay (in addition to Latency) to 50% of Data transition tLAT Latency in 1:2 Demux Non-DES DI, DQ Outputs 34 34 Mode(2) DId, DQd Outputs 35 35 Latency in 1:4 Demux DES DI Outputs 34 34 Mode(2) DQ Outputs 34.5 34.5 Sampling DId Outputs 35 35 Clock DQd Outputs 35.5 35.5 Cycles Latency in Non-Demux Non-DES DI Outputs 34 34 Mode(2) DQ Outputs 34 34 Latency in Non-Demux DES DI Outputs 34 34 Mode(2) DQ Outputs 34.5 34.5 tORR Over Range Recovery Time Differential VIN step from ±1.2V to Sampling 0V to accurate conversion 1 1 Clock Cycle (1) This parameter is specified by design and/or characterization and is not tested in production. (2) This parameter is specified by design and is not tested in production. 20 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: ADC12D1000 ADC12D1600 |
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