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ADC12D1000 Datasheet(PDF) 64 Page - Texas Instruments |
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ADC12D1000 Datasheet(HTML) 64 Page - Texas Instruments |
64 / 73 page ADC12D1000, ADC12D1600 SNAS480M – MAY 2010 – REVISED MARCH 2013 www.ti.com Table 20. Configuration Register 1 Addr: 0h (0000b) POR state: 2000h Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name CAL DPS OVS TPM PDI PDQ Res LFS DES DEQ DIQ 2SC TSE Res POR 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 CAL: Calibration Enable. When this bit is set to 1b, an on-command calibration is initiated. This bit is not reset automatically upon completion of the calibration. Therefore, the user must reset this bit to 0b and then set it to 1b again to execute another calibration. This bit is logically OR'd with the CAL Pin; both bit and pin must be set to 0b before either is used to execute a calibration. Bit 14 DPS: DCLK Phase Select. In DDR, set this bit to 0b to select the 0° Mode DDR Data-to-DCLK phase relationship and to 1b to select the 90° Mode. If the device is in Non-Demux Mode, this bit has no effect; the device will always be in 0°DDR Mode. Bit 13 OVS: Output Voltage Select. This bit sets the differential voltage level for the LVDS outputs including Data, OR, and DCLK. 0b selects the lower level and 1b selects the higher level. See VOD in Digital Control and Output Pin Characteristics for details. Bit 12 TPM: Test Pattern Mode. When this bit is set to 1b, the device will continually output a fixed digital pattern at the digital Data and OR outputs. When set to 0b, the device will continually output the converted signal, which was present at the analog inputs. See Test Pattern Mode for details about the TPM pattern. Bit 11 PDI: Power-down I-channel. When this bit is set to 0b, the I-channel is fully operational; when it is set to 1b, the I-channel is powered-down. The I-channel may be powered-down via this bit or the PDI Pin, which is active, even in ECM. Bit 10 PDQ: Power-down Q-channel. When this bit is set to 0b, the Q-channel is fully operational; when it is set to 1b, the Q-channel is powered-down. The Q-channel may be powered-down via this bit or the PDQ Pin, which is active, even in ECM. Bit 9 Reserved. Must be set to 0b. Bit 8 LFS: Low-Frequency Select. If the sampling clock (CLK) is at or below 300 MHz, set this bit to 1b for improved performance. Bit 7 DES: Dual-Edge Sampling Mode select. When this bit is set to 0b, the device will operate in the Non-DES Mode; when it is set to 1b, the device will operate in the DES Mode. See DES/Non-DES Mode for more information. Bit 6 DEQ: DES Q-input select, a.k.a. DESQ Mode. When the device is in DES Mode, this bit selects the input that the device will operate on. The default setting of 0b selects the I-input and 1b selects the Q-input. Bit 5 DIQ: DES I- and Q-input, a.k.a. DESIQ Mode. When in DES Mode, setting this bit to 1b shorts the I- and Q-inputs internally to the device. If the bit is left at its default 0b, the I- and Q-inputs remain electrically separate. To operate the device in DESIQ Mode, Bits<7:5> must be set to 101b. In this mode, both the I- and Q-inputs must be externally driven; see DES/Non-DES Mode for more information. Bit 4 2SC: Two's Complement output. For the default setting of 0b, the data is output in Offset Binary format; when set to 1b, the data is output in Two's Complement format. Bit 3 TSE: Time Stamp Enable. For the default setting of 0b, the Time Stamp feature is not enabled; when set to 1b, the feature is enabled. See Output Control and Adjust for more information about this feature. Bits 2:0 Reserved. Must be set as shown. Table 21. Reserved Addr: 1h (0001b) POR state: 2A0Eh Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Res POR 0 0 1 0 1 0 1 0 0 0 0 0 1 1 1 0 Bits 15:0 Reserved. Must be set as shown. 64 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: ADC12D1000 ADC12D1600 |
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