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5811 Datasheet(PDF) 4 Page - Allegro MicroSystems

Part No. 5811
Description  BiMOS II 12-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS
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Manufacturer  ALLEGRO [Allegro MicroSystems]
Direct Link  http://www.allegromicro.com
Logo ALLEGRO - Allegro MicroSystems

5811 Datasheet(HTML) 4 Page - Allegro MicroSystems

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115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
5811
BiMOS II 12-BIT
SERIAL-INPUT,
LATCHED SOURCE DRIVERS
Serial Data present at the input is transferred
to the shift register on the logic “0” to logic “1”
transition of the CLOCK input pulse. On
succeeding CLOCK pulses, the registers shift data
information towards the SERIAL DATA OUT-
PUT. The SERIAL DATA must appear at the
input prior to the rising edge of the CLOCK input
waveform.
Information present at any register is trans-
ferred to the respective latch when the STROBE
is high (serial-to-parallel conversion). The
latches will continue to accept new data as long as
the STROBE is held high. Applications where
the latches are bypassed (STROBE tied high) will
require that the BLANKING input be high during
serial data entry.
When the BLANKING input is high, the
output source drivers are disabled (OFF); the
DMOS sink drivers are ON, the information
stored in the latches is not affected by the
BLANKING input. With the BLANKING input
low, the outputs are controlled by the state of
their respective latches.
E
F
CLOCK
DATA IN
STROBE
BLANKING
OUTN
A
D
B
C
G
Dwg. No. 12,649A
TIMING REQUIREMENTS
(TA = +25°C,VDD = 5 V, Logic Levels are VDD and Ground)
A. Minimum Data Active Time Before Clock Pulse
(Data Set-Up Time) .......................................................................... 75 ns
B. Minimum Data Active Time After Clock Pulse
(Data Hold Time) ............................................................................. 75 ns
C. Minimum Data Pulse Width ................................................................ 150 ns
D. Minimum Clock Pulse Width ............................................................... 150 ns
E. Minimum Time Between Clock Activation and Strobe ....................... 300 ns
F. Minimum Strobe Pulse Width ............................................................. 100 ns
G. Typical Time Between Strobe Activation and
Output Transistion ......................................................................... 500 ns
Timing is representative of a 3.3 MHz clock. Higher speeds may be attainable
with increased supply voltage; operation at high temperatures will reduce the
specified maximum clock frequency.
TRUTH TABLE
Serial
Shift Register Contents
Serial
Latch Contents
Output Contents
Data
Clock
Data
Strobe
Input
Input I1
I2
I3
...
IN-1 IN
Output
Input
I1
I2
I3
...
IN-1 IN Blanklng
I1 I2 I3 ... IN-1 IN
HH
R1 R2 ...
RN-2 RN-1
RN-1
LL
R1 R2 ...
RN-2 RN-1
RN-1
XR1 R2 R3 ...
RN-1 RN
RN
XXX...
X
X
X
L
R1 R2 R3 ...
RN-1 RN
P1 P2 P3 ...
PN-1 PN
PN
HP1 P2 P3 ...
PN-1 PN
LP1 P2 P3 ... PN-1
PN
X
X
X
...
X
X
H
L
L
L
... L
L
L = Low Logic Level
H = High Logic Level
X = Irrelevant
P = Present State
R = Previous State


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