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APA075 Datasheet(PDF) 41 Page - Actel Corporation |
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APA075 Datasheet(HTML) 41 Page - Actel Corporation |
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41 / 178 page  ProASICPLUS Flash Family FPGAs v5.9 2-31 Operating Conditions Table 2-17 and Table 2-18 delineate operating limits. Performance Retention For devices operated and stored at 110°C or less, the performance retention period is 20 years after programming. For devices operated and stored at temperatures greater than 110°C, refer to Table 2-19 on page 2-32 to determine the performance retention period. Actel does not guarantee performance if the performance retention period is exceeded. Designers can determine the performance retention period from the following table. Evaluate the percentage of time spent at the highest temperature, then determine the next highest temperature to which the device will be exposed. In Table 2-19 on page 2-32, find the temperature profile that most closely matches the application. Example – the ambient temperature of a system cycles between 100°C (25% of the time) and 50°C (75% of the time). No forced ventilation cooling system is in use. An APA600-PQ208M FPGA operates in the system, dissipating 1 W. The package thermal resistance (junction-to-ambient) in still air Θja is 20°C/W, indicating that the junction temperature of the FPGA will be 120°C (25% of the time) and 70°C (75% of the time). The entry in Table 2-19 on page 2-32, which most closely matches the application, is 25% at 125°C with 75% at 110°C. Performance retention in this example is at least 16.0 years. Note that exceeding the stated retention period may result in a performance degradation in the FPGA below the worst-case performance indicated in the Actel Timer. To ensure that performance does not degrade below the worst-case values in the Actel Timer, the FPGA must be reprogrammed within the performance retention period. In addition, note that performance retention is independent of whether or not the FPGA is operating. The retention period of a device in storage at a given temperature will be the same as the retention period of a device operating at that junction temperature. Table 2-17 • Absolute Maximum Ratings* Parameter Condition Minimum Maximum Units Supply Voltage Core (VDD)–0.3 3.0 V Supply Voltage I/O Ring (VDDP)–0.3 4.0 V DC Input Voltage –0.3 VDDP + 0.3 V PCI DC Input Voltage –1.0 VDDP + 1.0 V PCI DC Input Clamp Current (absolute) VIN < –1 or VIN = VDDP + 1 V 10 mA LVPECL Input Voltage –0.3 VDDP + 0.5 V GND 00 V Note: *Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the Recommended Operating Conditions. Table 2-18 • Programming, Storage, and Operating Limits Product Grade Programming Cycles (min.) Program Retention (min.) Storage Temperature Operating Min. Max. TJ Max. Junction Temperature Commercial 500 20 years –55°C 110°C 110°C Industrial 500 20 years –55°C 110°C 110°C Military 100 Refer to Table 2-19 on page 2-32 –65°C 150°C 150°C MIL-STD-883 100 Refer to Table 2-19 on page 2-32 –65°C 150°C 150°C |
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