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APA1000 Datasheet(PDF) 36 Page - Actel Corporation |
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APA1000 Datasheet(HTML) 36 Page - Actel Corporation |
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36 / 174 page  ProASICPLUS Flash Family FPGAs 1- 32 v5.2 The following is an APA750 example using a shift register design with 13,440 storage tiles (Register) and 0 logic tiles. This design has one clock at 10 MHz, and 24 outputs toggling at 5 MHz. We then calculate the various components as follows: Pclock => Pclock = (P1 + (P2*R) - (P7*R 2)) * Fs = 121.5 mW Pstorage => Pstorage = P5 * ms * Fs = 147.8 mW Plogic => Plogic = 0 mW Poutputs => Poutputs = (P4 + (Cload * VDDP 2)) * p * Fp = 91.4 mW Pinputs => Pinputs = P8 * q * Fq = 0.3 mW Pmemory => Pmemory = 0 mW Pac => 361 mW Ptotal Pdc + Pac = 374 mW (typical) Fs = 10 MHz R = 13,440 ms = 13,440 (in a shift register 100% of storage tiles are toggling at each clock cycle and Fs = 10 MHz) mc = 0 (no logic tiles in this shift register) Cload = 40 pF VDDP = 3.3 V p= 24 Fp = 5 MHz q= 1 Fq = 10 MHz Nmemory = 0 (no RAM/FIFO blocks in this shift register) |
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