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APA075 Datasheet(PDF) 58 Page - Actel Corporation |
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APA075 Datasheet(HTML) 58 Page - Actel Corporation |
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58 / 174 page  ProASICPLUS Flash Family FPGAs 1- 54 v5.2 Embedded Memory Specifications This section discusses ProASICPLUS SRAM/FIFO embedded memory and its interface signals, including timing diagrams that show the relationships of signals as they pertain to single embedded memory blocks (Table 1-49). Table 1-12 on page 1-23 shows basic SRAM and FIFO configurations. Simultaneous read and write to the same location must be done with care. On such accesses the DI bus is output to the DO bus. Refer to the ProASICPLUS RAM and FIFO Blocks application note for more information. Enclosed Timing Diagrams—SRAM Mode: • "Synchronous SRAM Read, Access Timed Output Strobe (Synchronous Transparent)" section on page 1-55 • "Synchronous SRAM Read, Pipeline Mode Outputs (Synchronous Pipelined)" section on page 1-56 • "Asynchronous SRAM Write" section on page 1-57 • "Asynchronous SRAM Read, Address Controlled, RDB=0" section on page 1-58 • "Asynchronous SRAM Read, RDB Controlled" section on page 1-59 • "Synchronous SRAM Write" • Embedded Memory Specifications The difference between synchronous transparent and pipeline modes is the timing of all the output signals from the memory. In transparent mode, the outputs will change within the same clock cycle to reflect the data requested by the currently valid access to the memory. If clock cycles are short (high clock speed), the data requires most of the clock cycle to change to valid values (stable signals). Processing of this data in the same clock cycle is nearly impossible. Most designers add registers at all outputs of the memory to push the data processing into the next clock cycle. An entire clock cycle can then be used to process the data. To simplify use of this memory setup, suitable registers have been implemented as part of the memory primitive and are available to the user in the synchronous pipeline mode. In this mode, the output signals will change shortly after the second rising edge, following the initiation of the read access. Table 1-49 • Memory Block SRAM Interface Signals SRAM Signal Bits In/Out Description WCLKS 1 In Write clock used on synchronization on write side RCLKS 1 In Read clock used on synchronization on read side RADDR<0:7> 8 In Read address RBLKB 1 In True read block select (active Low) RDB 1 In True read pulse (active Low) WADDR<0:7> 8 In Write address WBLKB 1 In Write block select (active Low) DI<0:8> 9 In Input data bits <0:8>, <8> can be used for parity In WRB 1 In Negative true write pulse DO<0:8> 9 Out Output data bits <0:8>, <8> can be used for parity Out RPE 1 Out Read parity error (active High) WPE 1 Out Write parity error (active High) PARODD 1 In Selects Odd parity generation/detect when high, Even when low Note: Not all signals shown are used in all modes. |
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