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APA075-TQ144I Datasheet(PDF) 76 Page - Actel Corporation |
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APA075-TQ144I Datasheet(HTML) 76 Page - Actel Corporation |
76 / 174 page ProASICPLUS Flash Family FPGAs 1- 72 v5.2 FIFO Reset Notes: 1. During rest, the enables (WRB and RBD) must be high OR the clocks (WCLKS and RCKLS) must be low. 2. The plot shows the normal operation status. Figure 1-48 • FIFO Reset Table 1-66 • TJ = 0°C to 110°C; VDD = 2.3 V to 2.7 V for Commercial/industrial TJ = –55°C to 150°C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883 Symbol txxx Description Min. Max. Units Notes CBRSH1 WCLKS or RCLKS ↑ hold from RESETB ↑ 1.5 ns Synchronous mode only CBRSS1 WCLKS or RCLKS ↓ setup to RESETB ↑ 1.5 ns Synchronous mode only ERSA New EMPTY ↑ access from RESETB ↓ 3.0 ns FRSA FULL ↓ access from RESETB ↓ 3.0 ns RSL RESETB low phase 7.5 ns THRSA EQTH or GETH access from RESETB ↓ 4.5 ns WBRSH1 WB ↓ hold from RESETB ↑ 1.5 ns Asynchronous mode only WBRSS1 WB ↑ setup to RESETB ↑ 1.5 ns Asynchronous mode only Notes: 1. During rest, the enables (WRB and RBD) must be high OR the clocks (WCLKS and RCKLS) must be low. 2. All –F speed grade devices are 20% slower than the standard numbers. RESETB EMPTY EQTH, GETH FULL WRB/RBD1 Cycle Start Cycle Start WCLKS, RCLKS1 tERSA, tFRSA tTHRSA tCBRSS tWBRSS tCBRSH tWBRSH tRSL |
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