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SN65LVDS822RGZR Datasheet(PDF) 6 Page - Texas Instruments |
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SN65LVDS822RGZR Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 27 page  SN65LVDS822 SLLSEE8A – SEPTEMBER 2013 – REVISED OCTOBER 2013 www.ti.com TERMINAL FUNCTIONS (continued) NAME NO. I/O DESCRIPTION Selects the CMOS output pinout, and also controls differential input termination. Low – Default pinout, RID connected SWAP 45 Floating – Default pinout, RID disconnected (requires external termination) High – Swapped pinout, RID connected Sets the number of LVDS serial bits per lane per clock period. MODE14 36 Low – 7 bits (see Figure 8) High – 14 bits; only lanes A0 and A2 are used (see Figure 9) CLKOUT polarity CMOS Input Low – D[26:0] is valid during the CLKOUT falling edge CLKPOL 23 Floating – Reserved; do not use High – D[26:0] is valid during the CLKOUT rising edge SHTDN# 37 Shutdown Mode; Active-Low Sets the CMOS output slew rate Low – Slowest rise/fall time SLEW 35 Floating – Medium rise/fall time High – Fastest rise/fall time VDD 24, 44 Main power supply; 3.3 V VDDIO 6, 17, 43 Power Supply Power supply for CMOS outputs; 1.8 V to 3.3 V GND Thermal Pad Reference Ground 6 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links :SN65LVDS822 |
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