ONET1151L

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SLLSEI7 – DECEMBER 2013

where

•

ADCx = the decimal value read from the ADC

•

T_cal = the calibration temperature

•

ADC_cal = the decimal value read from the ADC at the calibration temperature

(8)

For the photodiode and bias current monitors, a nonzero current must be applied to the ADC in order to read

back a valid result. For the cases when the bias current is set to zero, the DIS pin is set high or the ENA bit is set

to 0, bias current is not applied to the ADC and the digital reading is not valid.

2-WIRE INTERFACE AND CONTROL LOGIC

The ONET1151L device uses a 2-wire serial interface for digital control. The two circuit inputs, SDA and SCK,

are driven, respectively, by the serial data and serial clock from a microprocessor, for example. The SDA and

SCK pins have internal 10-k

Ω pullups to VCC. If a common interface is used to control multiple parts, the internal

pullups can be switched to 40 k

Ω by setting the TWITERM bit to 1 (bit 0 of register 1). The internal pullups

automatically switch to 40 k

Ω, if the slave address is changed from its default value using the ADR0 or ADR1

pins.

The 2-wire interface allows write access to the internal memory map to modify control registers and read access

to read the control signals. The ONET1151L device is a slave device, which means that it cannot initiate a

transmission itself. The ONET1151L device always relies on the availability of the SCK signal for the duration of

the transmission. The master device provides the clock signal as well as the START and STOP commands. The

protocol for a data transmission is as follows:

1. START command

2. 7-bit slave address (0001000) followed by an eighth bit, which is the data direction bit (R/W). 0 indicates a

Write and 1 indicates a Read.

3. 8-bit register address

4. 8-bit register data word

5. STOP command

The first 2 bits of the slave address can be changed to 1 by grounding the ADR0 and ADR1 pins.

complete data transfer. Table 4 lists parameters for Figure 2.

Descriptions of various events on the 2-wire interface follow:

Bus idle: Both SDA and SCK lines remain High.

Start data transfer: A change in the state of the SDA line, from High to Low, while the SCK line is High, defines

a Start condition (S). Each data transfer initiates with a Start condition.

Stop data transfer: A change in the state of the SDA line from Low to High while the SCK line is High, defines a

Stop condition (P). Each data transfer is terminated with a Stop condition. However, if the master still wishes to

communicate on the bus, it can generate a repeated Start condition and address another slave without first

generating a Stop condition.

Data transfer: Only one data byte can be transferred between a Start and a Stop condition. The receiver

acknowledges the transfer of data.

Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge bit. The

transmitter releases the SDA line and a device that acknowledges must pull down the SDA line during the

acknowledge clock pulse so that the SDA line is stable Low during the High period of the acknowledge clock

pulse. Setup and hold times must be taken into account. When a slave-receiver does not acknowledge the slave

address, the data line must be left High by the slave. The master can then generate a Stop condition to abort the

transfer. If the slave-receiver does acknowledge the slave address, but some time later in the transfer cannot

receive any more data bytes, the master must abort the transfer. The slave indicates by generating no

acknowledgment on the first byte to follow. The slave leaves the data line High, and the master generates the

Stop condition.

Copyright © 2013, Texas Instruments Incorporated

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