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LMZ30604RKGT Datasheet(PDF) 5 Page - Texas Instruments |
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LMZ30604RKGT Datasheet(HTML) 5 Page - Texas Instruments |
5 / 25 page LMZ30604 www.ti.com SNVS998 – JULY 2013 PIN DESCRIPTIONS TERMINAL DESCRIPTION NAME NO. 1 Zero VDC reference for the analog control circuitry. These pins should be connected directly to the PCB 5 analog ground plane. Not all pins are connected together internally. All pins must be connected together AGND 29 externally with a copper plane or pour directly under the module. Connect the AGND copper area to the PGND copper area at a single point; directly at the pin 37 PowerPAD using multiple vias. See the 33 recommended layout in Figure 36. 34 This pad provides both an electrical and thermal connection to the PCB. This pad should be connected PowerPAD directly to the PCB power ground plane using multiple vias for good electrical and thermal performance. The 37 (PGND) same vias should also be used to connect to the PCB analog ground plane. See the recommended layout in Figure 36. 2 3 Do not connect. Do not connect these pins to AGND, to another DNC pin, or to any other voltage. These DNC 15 pins are connected to internal circuitry. Each pin must be soldered to an isolated pad. 16 26 Inhibit and UVLO adjust pin. Use an open drain or open collector output logic to control the INH function. A INH/UVLO 28 resistor between this pin and AGND adjusts the UVLO voltage. 17 18 19 20 21 Phase switch node. These pins should be connected by a small copper island under the device for thermal PH relief. Do not connect any external component to this pin or tie it to a pin of another function. 22 23 24 25 39 PWRGD 27 Power good fault pin. Asserts low if the output voltage is out of tolerance. A pull-up resistor is required. This pin automatically selects between RT mode and CLK mode. An external timing resistor adjusts the RT/CLK 4 switching frequency of the device. In CLK mode, the device synchronizes to an external clock. Remote sense connection. Connect this pin to VOUT at the load for improved regulation. This pin must be SENSE+ 36 connected to VOUT at the load, or at the module pins. Slow-start and tracking pin. Connecting an external capacitor to this pin adjusts the output voltage rise time. SS/TR 6 A voltage applied to this pin allows for tracking and sequencing control. Slow-start or track feature select. Connect this pin to AGND to enable the internal SS capacitor with a SS STSEL 7 interval of approximately 1.1 ms. Leave this pin open to enable the TR feature. VADJ 35 Connecting a resistor between this pin and AGND sets the output voltage above the 0.8V default voltage. 30 The positive input voltage power pins, which are referenced to PGND. Connect external input capacitance VIN 31 between these pins and the PGND plane, close to the device. 32 8 9 10 11 VOUT Output voltage. Connect output capacitors between these pins and the PGND plane, close to the device. 12 13 14 38 Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: LMZ30604 |
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