DS90UA102-Q1

SNLS442A – JULY 2013 – REVISED SEPTEMBER 2013

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ELECTRICAL CHARACTERISTICS:

Deserializer Switching Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.

(1) (2) (3)

Symbol

Parameter

Conditions

Pin/Freq.

Min

Typ

Max

Units

Receiver Output

STP Cable

SCK (Figure 9)

20

T

100

ns

Clock Period

Coaxial Cable

20

T

40

SCK Duty Cycle

SCK

40

50

60

%

LVCMOS Low-to-

SCK

1.3

2

2.8

High Transition Time to 3.6V,

ns

LVCMOS High-to-

Default Registers

1.3

2

2.8

Low Transition Time

(Figure 7),(4)

LVCMOS Low-to-

DOUT[7:0], GPO[3:0],

1

2.5

4

High Transition Time to 3.6V,

BCK, LRCK

ns

LVCMOS High-to-

Default Registers

1

2.5

4

Low Transition Time

(Figure 7),(4)

Setup Data to SCK

DOUT[7:0], GPO[3:0],

0.38

0.5

to 3.6V,

BCK, LRCK

Hold Data to SCK

T

0.38

0.5

Default Registers (Figure 9)

Default Registers

Deserializer Delay

Register 0x03h b[0] (RRFB = 1)

109

112

T

(Figure 8),(4)

Deserializer Data

With Adaptive Equalization

15

22

ms

Lock Time

(Figure 6)

SCK = 50 MHz

22

35

ps

Deserializer Period

SCK = 50 MHz

180

330

ps

Jitter

Deserializer Cycle-

SCK = 50 MHz

460

730

ps

to-Cycle Clock Jitter

(1)

The Electrical Characteristics tables list verified specifications under the listed Recommended Operating Conditions except as otherwise

modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not

verified.

(2)

Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground

(3)

the time of product characterization and are not verified .

(4)

Specification is verified by characterization and is not tested in production.

(5)

(6)

10

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