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DRV8332-HT Datasheet(PDF) 7 Page - Texas Instruments |
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DRV8332-HT Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 25 page  DRV8332-HT www.ti.com SLES274B – AUGUST 2013 – REVISED JANUARY 2014 ELECTRICAL CHARACTERISTICS TJ = -55°C to 175°C, PVDD = 50 V, GVDD = VDD = 12 V, fSw = 380 kHz, unless otherwise noted. All performance is in accordance with recommended operating conditions unless otherwise specified. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Internal Voltage Regulator and Current Consumption VREG Voltage regulator, only used as a reference node VDD = 12 V 2.85 3.3 3.75 V Idle, reset mode 9 15 mA IVDD VDD supply current Operating, 50% duty cycle 10.5 Reset mode 1.7 2.5 mA IGVDD_X Gate supply current per half-bridge Operating, 50% duty cycle 8 IPVDD_X Half-bridge X (A, B, or C) idle current Reset mode 0.7 1 mA Output Stage MOSFET drain-to-source resistance, low side (LS) TJ = 25°C, GVDD = 12 V 260 m Ω RDS(on) MOSFET drain-to-source resistance, high side (HS) TJ = 25°C, GVDD = 12 V 260 m Ω VF Diode forward voltage drop TJ = 25°C - 125°C, IO = 5 A 1 V tR Output rise time Resistive load, IO = 5 A 14 ns tF Output fall time Resistive load, IO = 5 A 14 ns tPD_ON Propagation delay when FET is on Resistive load, IO = 5 A 38 ns tPD_OFF Propagation delay when FET is off Resistive load, IO = 5 A 38 ns tDT Dead time between HS and LS FETs Resistive load, IO = 5 A 5.5 ns I/O Protection Gate supply voltage GVDD_X undervoltage Vuvp,G 8.5 V protection threshold Vuvp,hyst (1) Hysteresis for gate supply undervoltage event 0.3 V IOC Overcurrent limit protection Resistor—programmable, nominal, ROCP = 36 kΩ 7.4 A Time from application of short condition to Hi-Z of IOCT Overcurrent response time 250 ns affected FET(s) Static Digital Specifications VIH High-level input voltage PWM_A, PWM_B, PWM_C, M1, M2, M3 2 3.6 V VIH High-level input voltage RESET_A, RESET_B, RESET_C 2 3.6 V PWM_A, PWM_B, PWM_C, M1, M2, M3, VIL Low-level input voltage 0.8 V RESET_A, RESET_B, RESET_C llkg Input leakage current -100 100 μA OTW / FAULT Internal pullup resistance, OTW to VREG, FAULT to RINT_PU 20 26 35 k Ω VREG VOH High-level output voltage Internal pullup resistor only 1.95 3.3 3.65 V VOL Low-level output voltage IO = 4 mA 0.2 0.4 V (1) Specified by design Copyright © 2013–2014, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: DRV8332-HT |
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