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CAB4A Datasheet(PDF) 4 Page - Texas Instruments |
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CAB4A Datasheet(HTML) 4 Page - Texas Instruments |
4 / 10 page CAB4A SNAS630B – JULY 2013 – REVISED OCTOBER 2013 www.ti.com Table 1. TERMINAL FUNCTIONS (continued) SIGNAL TYPE DESCRIPTION GROUP NAME QACKE0/1, QAODT0/1, Register output CKE and ODT signals. QBCKE0/1, QBODT0/1 QACS0_n..QACS 1_n, Register output Chip Select signals. QBCS0_n..QBCS 1_n Output Control Bus Register output Chip Select signals. These pins initiate DRAM QACS2_n..QACS address/command decodes, and as such exactly one will be 3_n, LOW when a valid address/command is present which should QBCS2_n..QBCS be re-driven. 3_n or Some of these have alternative functions (Chip ID): QAC0..QAC1, • QxCS2_n ↔ QxC0 QBC0..QBC1 • QxCS2_n ↔ QxC0 QAC2, QBC2 Register output Chip ID2 signals. CMOS QAA0..QAA13, QAA17, QBA0..QBA13, QBA17, Outputs of the register, valid after the specified clock count and QABA0..QABA1, immediately following a rising edge of the clock. QBBA0..QBBA1, QAG0..QAG1, QBG0..QBG1 Outputs of the register, valid after the specified clock count and Output Address and QAA14..QAA16, immediately following a rising edge of the clock. Command bus QBA14..QBA16 In case of an ACT command some of these terminals have an or QAWE_n, alternative function: QACAS_n, QARAS_n, • QxA14 ↔ QxWE_n QBWE_n, • QxA15 ↔ QxCAS_n QBCAS_n, QBRAS_n • QxA16 ↔ QxRAS_n QAACT-n, Outputs of the register, valid after the specified clock count and QBACT_n immediately following a rising edge of the clock. Vref output QVREFCA VDD/2 Reference voltage Output reference voltage for DRAM receivers Y0_t..Y3_t, Clock outputs CMOS differential Re-driven clocks Y0_c..Y3_c Reset output QRST_n Re-driven reset. This is not an asynchronous output. CMOS Parity outputs QAPAR, QBPAR Re-driven parity(4) When LOW, this output indicates that a parity error was identified associated with the address and/or command inputs Error out ALERT_n Open drain when parity checking is enabled or that the ERROR_IN_n input was asserted, regardless of whether parity checking is enabled or not. Open drain SDA I2C Data I/O SCL I2C Clock CMOS input I2C pins SA[2:0] I2C Address signals CMOS input BFUNC Reserved(5) CMOS input VDDSPD I2C power input Power input (4) I2C inputs: These inputs are 2.5V inputs, except BFUNC which is a 1.2V input. (5) BFUNC has an internal pull-down resistor of 120 k Ω to V. 4 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: CAB4A |
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