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S25FL116K0XNFI041 Datasheet(PDF) 7 Page - SPANSION |
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S25FL116K0XNFI041 Datasheet(HTML) 7 Page - SPANSION |
7 / 79 page November 6, 2013 S25FL116K_00_06 S25FL116K 7 Da ta Shee t (Prelim i nar y ) Figures Figure 3.1 Hold Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 3.2 Bus Master and Memory Devices on the SPI Bus – Single Bit Data Path . . . . . . . . . . . . . . . 17 Figure 3.3 Bus Master and Memory Devices on the SPI Bus – Dual Bit Data Path . . . . . . . . . . . . . . . . 17 Figure 3.4 Bus Master and Memory Devices on the SPI Bus – Quad Bit Data Path . . . . . . . . . . . . . . . 18 Figure 4.1 SPI Modes Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 4.2 Stand Alone Instruction Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 4.3 Single Bit Wide Input Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 4.4 Single Bit Wide Output Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 4.5 Single Bit Wide I/O Command without Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 4.6 Single Bit Wide I/O Command with Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 4.7 Dual Output Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 4.8 Quad Output Command without Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 4.9 Dual I/O Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 4.10 Quad I/O Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 5.1 Maximum Negative Overshoot Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 5.2 Maximum Positive Overshoot Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 5.3 Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 5.4 Input, Output, and Timing Reference Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 5.5 Power-Up Timing and Voltage Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 5.6 Power-Down and Voltage Drop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 5.7 Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 5.8 SPI Single Bit Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 5.9 SPI Single Bit Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 5.10 SPI MIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 5.11 Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 5.12 WP# Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 9.1 Read Status Register Command Sequence Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Figure 9.2 Write Enable (WREN 06h) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Figure 9.3 Write Enable for Volatile Status Register Command Sequence . . . . . . . . . . . . . . . . . . . . . . 57 Figure 9.4 Write Disable (WRDI 04h) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Figure 9.5 Write Status Registers Command Sequence Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Figure 9.6 Page Program Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Figure 9.7 Sector Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Figure 9.8 64 kB Block Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Figure 9.9 Chip Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Figure 9.10 Erase / Program Suspend Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Figure 9.11 Erase / Program Resume Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Figure 9.12 Read Data Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Figure 9.13 Fast Read Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Figure 9.14 Fast Read Dual Output Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Figure 9.15 Fast Read Quad Output Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Figure 9.16 Fast Read Dual I/O Command Sequence (Initial command or previous M5-4 ≠ 10). . . . . . . 66 Figure 9.17 Fast Read Dual I/O Command Sequence (Previous command set M5-4 = 10) . . . . . . . . . . 66 Figure 9.18 Fast Read Quad I/O Command Sequence (Initial command or previous M5-4 ≠10) . . . . . . 67 Figure 9.19 Fast Read Quad I/O Command Sequence (Previous command set M5-4 = 10). . . . . . . . . . 67 Figure 9.20 Set Burst with Wrap Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Figure 9.21 Continuous Read Mode Reset for Fast Read Dual or Quad I/O . . . . . . . . . . . . . . . . . . . . . . 69 Figure 9.22 Deep Power-Down Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Figure 9.23 Release from Deep-Power-Down Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Figure 9.24 Read Electronic Signature (RES ABh) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . 71 Figure 9.25 READ_ID (90h) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Figure 9.26 Read JEDEC ID Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Figure 9.27 Read SFDP Register Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Figure 9.28 Erase Security Registers Command Sequence. . . . . . . . . . . . . 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