ASAHI KASEI

[AKD5393 Rev.A]

<KM059101>

’00/05

- 4 -

1-2DIT (Optical Link)

PORT1 is used. DIT generates audio Bi-phase signal from received data and which is output through optical

connector (TOTX174). It is possible to connect AKM's D/A converter evaluation boards on the digital-amplifier,

which equips DIR input. There are two kinds of jumper setting depend on the SMODE1 and SMODE2 pin. The

interface signals are output from PORT2. (See the (4)). In case of using external clock through a BNC connector,

select EXT on JP11 (MCLK) and short JP12 (XTE).

[Slave mode] (Default)

[Master mode]

Figure 3. Jumper set up (DIT)

1-3 All interface signals (MCLK, BICK and LRCK) are fed from external circuit. [Slave mode]

Under the following setup, MCLK, LRCK and SCLK signals needed for the A/D to operate could be

Fed through PORT2.

Figure 4. Jumper set up (EXT)

1-4 Feed all interface signals to the external circuit through PORT2.

[Master, Slave mode]

Please set up as same as 1-2. All interfacing signal which drive AK5393 are output through PORT2.

However, the FSYNC signal is input when the position of the SDATA is needed to be controlled.

* Setting for double speed sampling (fs=96kHz)

For the double speed sampling, DFS="L", MCLK=128fs, BICK=64fs(max) are required.

So, when BICK and LRCK are created from 74HC4040 on the board, the crystal oscillator should be changed to

24.576MHz and set JP14 (MCLK2) to 128fs side (see the schematics).

2. BIT CLK (BCF) set up

[JP8] Either 64fs or 128fs for the BCF can be selected. Figure shows 128fs example.

When DFS="H", set JP8 to 64 side.

128:

128fs is fed to AK5393 as BICK.

64:

64fs is fed to AK5393 as BICK.

JP9

JP7

BC

JP11

M CLK

EXT

XTL

JP12

XTE

LR

JP8

64

128

BCF

JP9

JP7

BC

JP11

MCLK

EXT

XTL

JP12

XTE

LR

JP9

JP7

BC

JP11

MCLK

EXT

XTL

JP12

XTE

LR