CAT93C66LI-G datasheet(3/16 Pages) ONSEMI

Part #	CAT93C66LI-G

Description	4 kb Microwire Serial CMOS EEPROM

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CAT93C66, CAT93W66

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Table 5. D.C. OPERATING CHARACTERISTICS − NEW PRODUCT (REV H)

(VCC = +1.8 V to +5.5 V, TA=−40°C to +125°C unless otherwise specified.)

Symbol

Parameter

Test Conditions

Min

Max

Units

ICC1

Supply Current (Write)

Write, VCC = 5.0 V

1

mA

ICC2

Supply Current (Read)

Read, DO open, fSK = 2 MHz, VCC = 5.0 V

500

mA

ISB1

Standby Current

(x8 Mode)

VIN = GND or VCC

CS = GND, ORG = GND

TA = −40°C to +85°C

2

mA

TA = −40°C to +125°C

5

ISB2

Standby Current

(x16 Mode)

VIN = GND or VCC

CS = GND,

ORG = Float or VCC

TA = −40°C to +85°C

1

mA

TA = −40°C to +125°C

3

ILI

Input Leakage Current

VIN = GND to VCC

TA = −40°C to +85°C

1

mA

TA = −40°C to +125°C

2

ILO

Output Leakage

Current

VOUT = GND to VCC

CS = GND

TA = −40°C to +85°C

1

mA

TA = −40°C to +125°C

2

VIL1

Input Low Voltage

4.5 V ≤ VCC < 5.5 V

−0.1

0.8

V

VIH1

Input High Voltage

4.5 V ≤ VCC < 5.5 V

2

VCC + 1

V

VIL2

Input Low Voltage

1.8 V ≤ VCC < 4.5 V

0

VCC x 0.2

V

VIH2

Input High Voltage

1.8 V ≤ VCC < 4.5 V

VCC x 0.7

VCC + 1

V

VOL1

Output Low Voltage

4.5 V ≤ VCC < 5.5 V, IOL = 3 mA

0.4

V

VOH1

Output High Voltage

4.5 V ≤ VCC < 5.5 V, IOH = −400 mA

2.4

V

VOL2

Output Low Voltage

1.8 V ≤ VCC < 4.5 V, IOL = 1 mA

0.2

V

VOH2

Output High Voltage

1.8 V ≤ VCC < 4.5 V, IOH = −100 mA

VCC − 0.2

V

Table 6. PIN CAPACITANCE (TA = 25°C, f = 1.0 MHz, VCC = +5.0 V)

Symbol

Test

Conditions

Min

Typ

Max

Units

COUT (Note 5)

Output Capacitance (DO)

VOUT = 0 V

5

pF

CIN (Note 5)

Input Capacitance (CS, SK, DI, ORG)

VIN = 0 V

5

pF

5. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100

and JEDEC test methods.

Table 7. POWER−UP TIMING (Notes 6, 7)

Symbol

Parameter

Max

Units

tPUR

Power−up to Read Operation

1

ms

tPUW

Power−up to Write Operation

1

ms

6. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate

AEC−Q100 and JEDEC test methods.

7. tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.

Table 8. A.C. TEST CONDITIONS

Input Rise and Fall Times

≤ 50 ns

Input Pulse Voltages

0.4 V to 2.4 V

4.5 V ≤ VCC ≤ 5.5 V

Timing Reference Voltages

0.8 V, 2.0 V

4.5 V ≤ VCC ≤ 5.5 V

Input Pulse Voltages

0.2 VCC to 0.7 VCC

1.8 V ≤ VCC ≤ 4.5 V

Timing Reference Voltages

0.5 VCC

1.8 V ≤ VCC ≤ 4.5 V

Output Load

Current Source IOLmax/IOHmax; CL = 100 pF

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