TMS320C6412AGDK5 datasheet(11/163 Pages) TI1

Part #	TMS320C6412AGDK5

Description	TMS320C6412 Fixed-Point Digital Signal Processor

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11 / 163 page

Tables

11

April 2003 − Revised October 2010

SPRS219J

Table

Page

4−5

Switching Characteristics Over Recommended Operating Conditions for CLKOUT4

106

. . . . . . . . . . . . .

4−6

Switching Characteristics Over Recommended Operating Conditions for CLKOUT6

107

. . . . . . . . . . . . .

4−7

Timing Requirements for AECLKIN for EMIFA

108

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−8

Switching Characteristics Over Recommended Operating Conditions for AECLKOUT1

for the EMIFA Module

108

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−9

Switching Characteristics Over Recommended Operating Conditions for AECLKOUT2

for the EMIFA Module

109

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−1

Timing Requirements for Asynchronous Memory Cycles for EMIFA Module

110

. . . . . . . . . . . . . . . . . . . .

5−2

Switching Characteristics Over Recommended Operating Conditions for Asynchronous

Memory Cycles for EMIFA Module

110

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6−1

Timing Requirements for Programmable Synchronous Interface Cycles for EMIFA Module

113

. . . . . . .

6−2

Switching Characteristics Over Recommended Operating Conditions for Programmable

Synchronous Interface Cycles for EMIFA Module

113

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7−1

Timing Requirements for Synchronous DRAM Cycles for EMIFA Module

117

. . . . . . . . . . . . . . . . . . . . . .

7−2

Switching Characteristics Over Recommended Operating Conditions for Synchronous

DRAM Cycles for EMIFA Module

117

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8−1

Timing Requirements for the HOLD/HOLDA Cycles for EMIFA Module

123

. . . . . . . . . . . . . . . . . . . . . . . .

8−2

Switching Characteristics Over Recommended Operating Conditions for the

HOLD/HOLDA Cycles for EMIFA Module

123

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9−1

Switching Characteristics Over Recommended Operating Conditions for the

BUSREQ Cycles for EMIFA Module

124

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10−1

Timing Requirements for Reset

125

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10−2

Switching Characteristics Over Recommended Operating Conditions During Reset

125

. . . . . . . . . . . . .

11−1

Timing Requirements for External Interrupts

127

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12−1

Timing Requirements for I2C Timings

128

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12−2

Switching Characteristics for I2C Timings

129

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13−1

Timing Requirements for Host-Port Interface Cycles

130

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13−2

Switching Characteristics Over Recommended Operating Conditions During

Host-Port Interface Cycles)

130

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14−1

Timing Requirements for PCLK†‡ (see Figure 14−1)

135

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14−2

Timing Requirements for PCI Reset (see Figure 14−2)

135

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14−3

Timing Requirements for PCI Inputs (see Figure 14−3)

136

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14−4

Switching Characteristics Over Recommended Operating Conditions for PCI Outputs

136

. . . . . . . . . . .

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