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TMS27C128-2JE Datasheet(PDF) 9 Page - Texas Instruments |
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TMS27C128-2JE Datasheet(HTML) 9 Page - Texas Instruments |
9 / 14 page TMS27C128 131 072-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY TMS27PC128 131 072-BIT PROGRAMMABLE READ-ONLY MEMORY SMLS128E–OCTOBER 1984–REVISED JANUARY 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 9 switching characteristics over full ranges of recommended operating conditions (see Notes 3 and 4) PARAMETER TEST CONDITIONS ’27C128-12 ’27C/PC128-15 UNIT PARAMETER TEST CONDITIONS (SEE NOTES 3 AND 4) MIN MAX MIN MAX UNIT ta(A) Access time from address 120 150 ns ta(E) Access time from chip enable CL = 100 pF 120 150 ns ten(G) Output enable time from G CL = 100 F, 1 Series 74 TTL Load, 55 75 ns tdis Output disable time from G or E, whichever occurs first† Input tr ≤ 20 ns, Input tf ≤ 20 ns 0 45 0 60 ns tv(A) Output data valid time after change of address, E, or G, whichever occurs first† In ut tf ≤ 20 ns 0 0 ns TEST CONDITIONS ’27C/PC128-20 ′27C/PC128-25 UNIT (SEE NOTES 3 AND 4) MIN MAX MIN MAX UNIT ta(A) Access time from address 200 250 ns ta(E) Access time from chip enable CL = 100 pF 200 250 ns ten(G) Output enable time from G CL = 100 F, 1 Series 74 TTL Load, 75 100 ns tdis Output disable time from Go r E, whichever occurs first† Input tr ≤ 20 ns, Input tf ≤ 20 ns 0 60 0 60 ns tv(A) Output data valid time after change of address, E, or G, whichever occurs first† In ut tf ≤ 20 ns 0 0 ns † Value calculated from 0.5 V delta to measured level. This parameter is only sampled and not 100% tested. switching characteristics for programming:VCC = 6.5 V and VPP = 13 V (SNAP! Pulse), TA = 25°C (see Note 3) PARAMETER MIN NOM MAX UNIT tdis(G) Output disable time from G 0 130 ns ten(G) Output enable time from G 150 ns recommended timing requirements for programming: VCC = 6.5 V and VPP =13 V (SNAP! Pulse), TA = 25°C (see Note 3) MIN NOM MAX UNIT tw(IPGM) Initial program pulse duration SNAP! Pulse programming algorithm 95 100 105 µs tsu(A) Address setup time 2 µs tsu(E) E setup time 2 µs tsu(G) G setup time 2 µs tsu(D) Data setup time 2 µs tsu(VPP) VPP setup time 2 µs tsu(VCC) VCC setup time 2 µs th(A) Address hold time 0 µs th(D) Data hold time 2 µs NOTES: 3. For all switching characteristics the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and 0.8 V for logic low (reference page 10). 4. Common test conditions apply for tdis except during programming. |
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