SN75C198

QUADRUPLE LOW-POWER LINE DRIVERS

SLLS051C – JULY 1990 – REVISED MARCH 1997

5

POST OFFICE BOX 655303

SM at 2 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP†

MAX

UNIT

VOH

High level output voltage

VIH =0 8V

RL =3kΩ

VCC

± = ±5 V

4

V

VOH

High-level output voltage

VIH = 0.8 V,

RL = 3 kΩ

VCC

± = ±12 V

10

V

VOL

Low level output voltage (see Note 2)

VIH =2V

RL =3kΩ

VCC

± = ±5 V

–4

V

VOL

Low-level output voltage (see Note 2)

VIH = 2 V,

RL = 3 kΩ

VCC

± = ±12 V

–10

V

IIH

High-level input current

VI = 5 V

10

µA

IIL

Low-level input current

VI = 0 V

–10

µA

VO = 12 V,

100

IOZ

High impedance state output current

SM at 0 6 V

O

,

VCC

± = ±12 V

100

µA

IOZ

High-impedance-state output current

SM at 0.6 V

VO = – 12 V,

100

µA

O

,

VCC

± = ±12 V

– 100

IOS(H)

High-level short-circuit output current‡

VI = 0.8 V,

VO = 0 or VCC –

– 4.5

–10

– 19.5

mA

IOS(L)

Low-level short-circuit output current‡

VI = 2 V,

VO = 0 or VCC +

4.5

10

19.5

mA

ro

Output resistance

VCC

± = 0,

VO = – 2 V to 2 V

300

Ω

A and B inputs at 0.8 V or 2 V,

VCC

± = ±5 V

90

160

ICC

Supply current from VCC

,

No load

VCC

± = ±12 V

95

160

µA

ICC +

Supply current from VCC +

A and B inputs at 0.8 V or 2 V,

VCC

± = ±5 V

40

µA

,

RL = 3 kΩ,SM at 0.6 V

VCC

± = ±12 V

40

A and B inputs at 0.8 V or 2 V,

VCC

± = ±5 V

–90

– 160

ICC

Supply current from VCC

,

No load

VCC

± = ±12 V

–95

– 160

µA

ICC –

Supply current from VCC –

A and B inputs at 0.8 V or 2 V,

VCC

± = ±5 V

–40

µA

RL = 3 kΩ,SM at 0.6 V

VCC

± = ±12 V

–40

† All typical values are at TA = 25°C.

‡ Not more than one output should be shorted at a time.

NOTE 2: The algebraic convention, where the more positive (less negative) limit is designated as maximum, is used in this data sheet for logic

levels only, e.g., if – 10 V is a maximum, the typical value is a more negative voltage.

(unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP†

MAX

UNIT

tPLH

Propagation delay time, low- to high-level output§

3

µs

tPHL

Propagation delay time, high- to low-level output§

RL = 3 kΩ to 7 kΩ,

CL = 15 pF,

3.5

µs

tTLH

Transition time, low- to high-level output¶

L

,

See Figure 1

L

,

0.53

1

3.2

µs

tTHL

Transition time, high- to low-level output¶

0.53

1

3.2

µs

tTLH

Transition time, low- to high-level output#

RL = 3 kΩ to 7 kΩ,

CL = 2500 pF,

1.5

µs

tTHL

Transition time, high- to low-level output#

L

,

See Figure 2

L

,

1.5

µs

tPZH

Output enable time to high level

RL = 3 kΩ to 7 kΩ,

CL = 15 pF,

50

µs

tPHZ

Output disable time from high level

L

,

See Figure 3

L

,

10

µs

tPZL

Output enable time to low level

RL = 3 kΩ to 7 kΩ,

CL = 15 pF,

15

µs

tPLZ

Output disable time from low level

L

,

See Figure 4

L

,

10

µs

SR

Output slew rate#

RL = 3 kΩ to 7 kΩ,

CL = 15 pF

6

15

30

V/

µs

† All typical values are at TA = 25°C.

§ tPHL and tPLH include the additional time due to on-chip slew rate and are measured at the 50% points.

¶ Measured between 10% and 90% points of output waveform

# Measured between 3-V and – 3-V points of output waveform