 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
AD6644STPCB Datasheet(PDF) 13 Page - Analog Devices |
|
||||||||||||||||||||||||||||||
AD6644STPCB Datasheet(HTML) 13 Page - Analog Devices |
|
|
13 / 28 page  HSC-ADC-EVALB-SC/HSC-ADC-EVALB-DC Rev. 0 | Page 13 of 28 EVALUATION BOARD The FIFO provides all of the support circuitry required to accept two channels of an ADC’s digital parallel CMOS outputs. Each of the various functions and configurations can be selected by proper connection of various jumpers (see Table 5). When using this in conjunction with an ADC evaluation board, it is critical that the signal sources used for the analog input and clock have very low phase noise (<1 ps rms jitter) to realize the ultimate performance of the converter. Proper filtering of the analog input signal to remove harmonics and lower the integrated or broadband noise at the input is also necessary to achieve the specified noise performance. See Figure 5 to Figure 15 for complete schematics and layout plots. POWER SUPPLIES The FIFO board is supplied with a wall mount switching power supply that provides a 6 V, 2 A maximum output. Connect the supply to the rated 100 ac to 240 ac wall outlet at 47 Hz to 63 Hz. The other end is a 2.1 mm inner diameter jack that connects to the PCB at J301. On the PC board, the 6 V supply is then fused and conditioned before connecting to the low dropout 3.3 V linear regulator that supplies the proper bias to the entire board. When operating the evaluation board in a non-default condition, J316 can be removed to disconnect the switching power supply. This enables the user to bias the board independently. Use P302 to connect an independent supply to the board. A 3.3 V supply is needed with at least a 1 A current capability. CONNECTION AND SETUP The FIFO board has a 120-pin (40-pin, triple row) connector that accepts two 16-bit channels of parallel CMOS inputs (see Figure 6). For those ADC evaluation boards that have only an 80-pin (40-pin, double row) connector, it is pertinent for the lower two rows of the FIFO’s triple row connector to be connected in order for the data to pass to either FIFO channel correctly. The top or third row is used to pass SPI signals across to the adjacent ADC evaluation board that supports this feature. ROHDE & SCHWARZ, SMHU, 2V p-p SIGNAL SYNTHESIZER ROHDE & SCHWARZ, SMHU, 2V p-p SIGNAL SYNTHESIZER BAND-PASS FILTER USB CONNECTION HSC-ADC-EVALB-DC FIFO DATA CAPTURE BOARD PC RUNNING ADC ANALYZER –+ 3.3V 6V DC 2A MAX WALL OUTLET 100V TO 240V AC 47Hz TO 63Hz CHB PARALLEL CMOS OUTPUTS EVALUATION BOARD CHB PARALLEL CMOS OUTPUTS XFMR INPUT CLK SWITCHING POWER SUPPLY SPI SPI SPI Figure 4. Example Setup Using Quad ADC Evaluation Board and FIFO Data Capture Board |
Similar Part No. - AD6644STPCB |
|
Similar Description - AD6644STPCB |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
