ASAHI KASEI

[AK4393]

M0039-E-01

2000/5

- 7 -

SWITCHING CHARACTERISTICS

(Ta = 25

°C; AVDD = 4.75~5.25V; DVDD = 3.0~5.25V; C

Parameter

Symbol

min

typ

max

Units

Master Clock Timing

Normal Speed: 256fs, Double Speed: 128fs

Pulse Width Low

Pulse Width High

fCLK

tCLKL

tCLKH

7.7

28

28

13.824

MHz

ns

ns

Normal Speed: 384fs, Double Speed: 192fs

Pulse Width Low

Pulse Width High

fCLK

tCLKL

tCLKH

11.5

20

20

20.736

MHz

ns

ns

Normal Speed: 512fs, Double Speed: 256fs

Normal Speed: 768fs, Double Speed: 384fs

Pulse Width Low

Pulse Width High

fCLK

fCLK

tCLKL

tCLKH

15.4

23.0

7

7

27.648

41.472

MHz

MHz

ns

ns

LRCK Frequency

(Note 17)

Normal Speed Mode (DFS = “L”)

Double Speed Mode (DFS = “H”)

Duty Cycle

fsn

fsd

Duty

30

60

45

44.1

88.2

54

108

55

kHz

kHz

%

Serial Interface Timing

BICK Period

BICK Pulse Width Low

Pulse Width High

BICK “

­” to LRCK Edge

(Note 18)

LRCK Edge to BICK “

­”

(Note 18)

SDATA Hold Time

SDATA Setup Time

tBCK

tBCKL

tBCKH

tBLR

tLRB

tSDH

tSDS

140

60

60

20

20

20

20

ns

ns

ns

ns

ns

ns

ns

Control Interface Timing

CCLK Period

CCLK Pulse Width Low

Pulse Width High

CDTI Setup Time

CDTI Hold Time

CSN High Time

CSN “

¯” to CCLK “­”

CCLK “

­” to CSN “­”

tCCK

tCCKL

tCCKH

tCDS

tCDH

tCSW

tCSS

tCSH

200

80

80

50

50

150

50

50

ns

ns

ns

ns

ns

ns

ns

ns

Reset Timing

PDN Pulse Width

(Note 19)

tPW

150

ns

Notes: 17. When the normal and double speed modes are switched, AK4393 should be reset by PDN pin or RSTN bit.

18. BICK rising edge must not occur at the same time as LRCK edge.

19. The AK4393 can be reset by bringing PDN “L” to “H”.

When the states of CKS2-0 or DFS change, the AK4393 should be reset by PDN pin or RSTN bit.