IN1

IN4

MUX

T/H

SCLK

GND

CS

DIN

DOUT

CONTROL

LOGIC

10-Bit

SUCCESSIVE

APPROXIMATION

ADC

.

.

.

GND

ADC104S051

SNAS253G – NOVEMBER 2004 – REVISED MARCH 2013

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Block Diagram

PIN DESCRIPTIONS and EQUIVALENT CIRCUITS

Pin No.

Symbol

Description

ANALOG I/O

4-7

IN1 to IN4

DIGITAL I/O

10

SCLK

Digital clock input. This clock directly controls the conversion and readout processes.

Digital data output. The output samples are clocked out of this pin on falling edges of the

9

DOUT

SCLK pin.

Digital data input. The ADC104S051's Control Register is loaded through this pin on rising

8

DIN

edges of the SCLK pin.

Chip select. On the falling edge of CS, a conversion process begins. Conversions continue

1

CS

as long as CS is held low.

POWER SUPPLY

Positive supply pin. This pin should be connected to a quiet +2.7V to +5.25V source and

2

bypassed to GND with a 1 µF capacitor and a 0.1 µF monolithic capacitor located within 1

cm of the power pin.

3

GND

The ground return for the supply and signals.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

2

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