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AD7674 Datasheet(PDF) 17 Page - Analog Devices

Part No. AD7674
Description  16-Bit, 250 kSPS CMOS ADC
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
Logo AD - Analog Devices

AD7674 Datasheet(HTML) 17 Page - Analog Devices

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REV. B
AD7663
–17–
PARALLEL INTERFACE
The AD7663 is configured to use the parallel interface when
the SER/
PAR is held LOW. The data can be read either after
each conversion, which is during the next acquisition phase, or
during the following conversion as shown, respectively, in
Figures 14 and 15. When the data is read during the conversion,
however, it is recommended that it be read-only during the
first half of the conversion phase. That avoids any potential
feedthrough between voltage transients on the digital interface and
the most critical analog conversion circuitry.
RD
BUSY
CS
CURRENT
CONVERSION
DATA BUS
t12
t13
Figure 14. Slave Parallel Data Timing for Reading (Read
after Convert)
t1
CS = 0
CNVST,
RD
PREVIOUS
CONVERSION
t3
t12
t13
t4
BUSY
DATA BUS
Figure 15. Slave Parallel Data Timing for Reading (Read
during Convert)
The BYTESWAP pin allows a glueless interface to an 8-bit bus.
As shown in Figure 16, the LSB byte is output on D[7:0] and
the MSB is output on D[15:8] when BYTESWAP is LOW.
When BYTESWAP is HIGH, the LSB and MSB are swapped
and the LSB is output on D[15:8] and the MSB is output on
D[7:0]. By connecting BYTESWAP to an address line, the 16
data bits can be read in two bytes on either D[15:8] or D[7:0].
CS
BYTE
PINS D[15:8]
HI-Z
HIGH BYTE
LOW BYTE
HI-Z
HI-Z
HIGH BYTE
LOW BYTE
HI-Z
t
12
t
12
t
13
RD
PINS D[7:0]
Figure 16. 8-Bit Parallel Interface
SERIAL INTERFACE
The AD7663 is configured to use the serial interface when the
SER/
PAR is held HIGH. The AD7663 outputs 16 bits of data,
MSB first, on the SDOUT pin. This data is synchronized with
the 16 clock pulses provided on the SCLK pin. The output data
is valid on both the rising and falling edge of the data clock.
MASTER SERIAL INTERFACE
Internal Clock
The AD7663 is configured to generate and provide the serial data
clock SCLK when the EXT/
INT pin is held LOW. It also generates
a SYNC signal to indicate to the host when the serial data is valid.
The serial clock SCLK and the SYNC signal can be inverted if
desired. Depending on RDC/SDIN input, the data can be read
after each conversion or during the following conversion. Figures 17
and 18 show the detailed timing diagrams of these two modes.
Usually, because the AD7663 has a longer acquisition phase
than the conversion phase, the data is read immediately after
conversion. That makes the mode master, read after conversion,
the most recommended Serial Mode when it can be used.
In Read-during-Conversion Mode, the serial clock and data
toggle at appropriate instants that minimize potential feedthrough
between digital activity and the critical conversion decisions.
In Read-after-Conversion Mode, it should be noted that unlike
in other modes, the signal BUSY returns LOW after the 16 data
bits are pulsed out and not at the end of the conversion phase,
which results in a longer BUSY width. In this mode, if neces-
sary, the internal clock can be slowed down by a ratio selected
by the DIVSCLK inputs according to Table II.


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