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AD7674 Datasheet(PDF) 15 Page - Analog Devices |
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AD7674 Datasheet(HTML) 15 Page - Analog Devices |
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15 / 24 page 
REV. B AD7663 –15– Voltage Reference Input The AD7663 uses an external 2.5 V voltage reference. The voltage reference input REF of the AD7663 has a dynamic input impedance; it should therefore be driven by a low impedance source with an efficient decoupling between REF and REFGND inputs. This decoupling depends on the choice of the voltage reference but usually consists of a 1 µF ceramic capacitor and a low ESR tantalum capacitor connected to the REF and REFGND inputs with minimum parasitic inductance. 47 µF is an appropriate value for the tantalum capacitor when used with one of the recommended reference voltages: • The low noise, low temperature drift ADR421 and AD780 voltage reference • The low power ADR291 voltage reference • The low cost AD1582 voltage reference For applications using multiple AD7663s, it is more effective to buffer the reference voltage with a low noise, very stable op amp like the AD8031. Care should also be taken with the reference temperature coefficient of the voltage reference that directly affects the full-scale accu- racy if this parameter matters. For instance, a ±15 ppm/°C tempco of the reference changes the full scale by ±1 LSB/°C. Note that VREF , as mentioned in the Specification tables, could be increased to AVDD – 1.85 V. The benefit here is the increased SNR obtained as a result of this increase. Since the input range is defined in terms of VREF, this would essentially increase the ±REF range from ±2.5 V to ±3 V and so on with an AVDD above 4.85 V. The theoretical improvement as a result of this increase in reference is 1.58 dB (20 log [3/2.5]). Due to the theoretical quantization noise, however, the observed improvement is approxi- mately 1 dB. The AD780 can be selected with a 3 V reference voltage. Scaler Reference Input (Bipolar Input Ranges) When using the AD7663 with bipolar input ranges, the connection diagram in Figure 5 shows a reference buffer amplifier. This buffer amplifier is required to isolate the REF pin from the signal dependent current in the INx pin. A high speed op amp, such as the AD8031, can be used with a single 5 V power supply with- out degrading the performance of the AD7663. The buffer must have good settling characteristics and provide low total noise within the input bandwidth of the AD7663. Power Supply The AD7663 uses three sets of power supply pins: an analog 5 V supply AVDD, a digital 5 V core supply DVDD, and a digital input/output interface supply OVDD. The OVDD supply allows direct interface with any logic working between 2.7 V and DVDD + 0.3 V. To reduce the number of supplies needed, the digital core (DVDD) can be supplied through a simple RC filter from the analog supply as shown in Figure 5. The AD7663 is independent of power supply sequencing, once OVDD does not exceed DVDD by more than 0.3 V, and thus free from supply voltage induced latch-up. Additionally, it is very insensitive to power supply variations over a wide frequency range as shown in Figure 9. 110 105 100 95 90 85 80 75 70 65 60 55 50 1 10 100 1000 FREQUENCY – kHz Figure 9. PSRR vs. Frequency POWER DISSIPATION The AD7663 automatically reduces its power consumption at the end of each conversion phase. During the acquisition phase, the operating currents are very low, which allows a significant power savings when the conversion rate is reduced as shown in Figure 10. This feature makes the AD7663 ideal for very low power battery applications. This does not take into account the power, if any, dissipated by the input resistive scaler that depends on the input voltage range used and the analog input voltage even in power-down mode. There is no power dissipated when the 0 V to 2.5 V is used or when both the analog input voltage is 0V and a unipolar range, 0V to 5 V or 0 V to 10 V, is used. It should be noted that the digital interface remains active even during the acquisition phase. To reduce the operating digital supply currents even further, the digital inputs need to be driven close to the power rails (i.e., DVDD and DGND) and OVDD should not exceed DVDD by more than 0.3 V. |
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