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AD7674 Datasheet(PDF) 7 Page - Analog Devices
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PIN FUNCTION DESCRIPTION (continued)
PAR is LOW, this output is used as Bit 8 of the Parallel Port Data Output Bus.
PAR is HIGH, this output, part of the Serial Port, is used as a serial data output
synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7663 provides
the conversion result, MSB first, from its internal shift register. The Data format is determined
by the logic level of OB/
2C. In Serial Mode, when EXT/INT is LOW, SDOUT is valid on both
edges of SCLK.
In serial mode, when EXT/
INT is HIGH:
If INVSCLK is LOW, SDOUT is updated on the SCLK rising edge and valid on the next falling edge.
If INVSCLK is HIGH, SDOUT is updated on the SCLK falling edge and valid on the next rising edge.
PAR is LOW, this output is used as Bit 9 of the Parallel Port Data Output Bus.
PAR is HIGH, this pin, part of the Serial Port, is used as a serial data clock input or
output, dependent upon the logic state of the EXT/
INT pin. The active edge where the data
SDOUT is updated depends upon the logic state of the INVSCLK pin.
PAR is LOW, this output is used as Bit 10 of the Parallel Port Data Output Bus.
PAR is HIGH, this output, part of the Serial Port, is used as a digital output frame
synchronization for use with the internal data clock (EXT/
INT = Logic LOW). When a read
sequence is initiated and INVSYNC is LOW, SYNC is driven HIGH and remains HIGH while
SDOUT output is valid. When a read sequence is initiated and INVSYNC is HIGH, SYNC is
driven LOW and remains LOW while SDOUT output is valid.
PAR is LOW, this output is used as Bit 11 of the Parallel Port Data Output Bus.
PAR is HIGH and EXT/INT is HIGH, this output, part of the Serial Port, is used as
an incomplete read error flag. In Slave Mode, when a data read is started and not complete when
the following conversion is complete, the current data is lost and RDERROR is pulsed HIGH.
Bit 12 to Bit 15 of the Parallel Port Data Output Bus. When SER/
PAR is HIGH, these outputs
are in high impedance.
Busy Output. Transitions HIGH when a conversion is started and remains HIGH until the
conversion is complete and the data is latched into the on-chip shift register. The falling edge
of BUSY could be used as a data-ready clock signal.
Must Be Tied to Digital Ground.
Read Data. When
CS and RD are both LOW, the Interface Parallel or Serial Output Bus is enabled.
Chip Select. When
CS and RD are both LOW, the Interface Parallel or Serial Output Bus is
CS is also used to gate the external clock.
Reset Input. When set to a logic HIGH, reset the AD7663. Current conversion, if any, is aborted.
If not used, this pin could be tied to DGND.
Power-Down Input. When set to a logic HIGH, power consumption is reduced and conversions
are inhibited after the current one is completed.
Start Conversion. If
CNVST is HIGH when the acquisition phase (t
) is complete, the next falling
CNVST puts the internal sample-and-hold into the hold state and initiates a conversion.
This mode is the most appropriate if low sampling jitter is desired. If
CNVST is LOW when the
acquisition phase (t
) is complete, the internal sample-and-hold is put into the hold state and a
conversion is immediately started.
Must Be Tied to Analog Ground.
Reference Input Voltage .
Reference Input Analog Ground.
Analog Input Ground.
Analog Inputs. Refer to Table I for input range configuration.
AI = Analog Input
DI = Digital Input
DI/O = Bidirectional Digital
DO = Digital Output
P = Power
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