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XRP6124HVES0.5-F Datasheet(PDF) 8 Page - Exar Corporation |
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XRP6124HVES0.5-F Datasheet(HTML) 8 Page - Exar Corporation |
8 / 12 page X XR RP P6 61 12 24 4 N No on n--S Sy yn nc ch hrro on no ou us s P PF FE ET T S Stte ep p--D Do ow wn n C Co on nttrro olllle err © 2011 Exar Corporation 8/12 Rev. 1.1.0 finished. If the feedback voltage drops below 0.55V, equivalent to output voltage dropping below 69% of nominal, the comparator will trip causing the IC to latch off. In order to restart the XRP6124, the input voltage has to be reduced below UVLO threshold and then increased to its normal operating point. SOFT -START To limit in-rush current the XRP6124 has an internal soft-start. The nominal soft-start time is 2ms and commences when VIN exceeds the UVLO threshold. As explained above, the short-circuit comparator is enabled as soon as soft-start is complete. Therefore if the input voltage has a very slow rising edge such that at the end of soft-start the output voltage has not reached 69% of its final value then the XRP6124 will latch-off. ENABLE By applying a logic-level signal to the enable pin EN the XRP6124 can be turned on and off. Pulling the enable below 1V shuts down the controller and reduces the VIN leakage current to 1.5µA nominal as seen in figure 18. Enable signal should always be applied after the input voltage or concurrent with it. Otherwise XRP6124 will latch up. In applications where an independent enable signal is not available, a Zener diode can be used to derive VEN from VIN. DISCONTINUOUS CONDUCTION MODE , DCM Because XRP6124 is a non-synchronous controller, when load current IOUT is reduced to less than half of peak-to-peak inductor current ripple ΔIL, the converter enters DCM mode of operation. The switching frequency fs is now IOUT dependent and no longer governed by the relationship shown in table 2. As IOUT is decreased so does fs until a minimum switching frequency, typically in the range of few hundred Hertz, is reached at no load. This contributes to good converter efficiency at light load as seen in figures 4 and 5. The reduced fs corresponding to light load, however, increases the output voltage ripple and causes a slight increase in output voltage as seen in figures 8 and 9. Another effect of reduced fs at light load is slow down of transient response when a load step transitions from a high load to a light load. This is shown in figures 16 and 17. APPLICATION INFORMATION SETTING THE OUTPUT VOLTAGE Use an external resistor divider to set the output voltage. Program the output voltage from: ⎟ ⎠ ⎞ ⎜ ⎝ ⎛ − × = 1 8 . 0 2 1 OUT V R R where: R1 is the resistor between VOUT and FB R2 is the resistor between FB and GND (nominally 2kΩ) 0.8V is the nominal feedback voltage. FEED -FORWARD CAPACITOR CFF CFF, which is placed in parallel with R1, provides a low-impedance/high-frequency path for the output voltage ripple to be transmitted to FB. It also helps get an optimum transient response. An initial value for CFF can be calculated from: 1 1 . 0 2 1 R fs CFF × × × × = π where: fs is the switching frequency from table 2 This value can be adjusted as necessary to provide an optimum load step transient response. |
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