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PIC24FJ48GA004 Datasheet(PDF) 10 Page - Microchip Technology |
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PIC24FJ48GA004 Datasheet(HTML) 10 Page - Microchip Technology |
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10 / 52 page  PIC24FJXXXGA0XX DS39768D-page 10 © 2008 Microchip Technology Inc. 2.4 Memory Map The program memory map extends from 000000h to FFFFFEh. Code storage is located at the base of the memory map and supports up to 44K instruction words (about 128 Kbytes). Table 2-3 shows the program memory size and number of erase and program blocks present in each device variant. Each erase block, or page, contains 512 instructions, and each program block, or row, contains 64 instructions. Locations 800000h through 8007FEh are reserved for executive code memory. This region stores the programming executive and the debugging executive. The programming executive is used for device pro- gramming and the debugging executive is used for in-circuit debugging. This region of memory can not be used to store user code. The last two implemented program memory locations are reserved for the device Configuration registers. TABLE 2-2: FLASH CONFIGURATION WORD LOCATIONS FOR PIC24FJXXXGA0XX DEVICES Locations, FF0000h and FF0002h, are reserved for the Device ID registers. These bits can be used by the programmer to identify what device type is being programmed. They are described in Section 6.1 “Device ID”. The Device ID registers read out normally, even after code protection is applied. Figure 2-4 shows the memory map for the PIC24FJXXXGA0XX family variants. TABLE 2-3: CODE MEMORY SIZE Device Configuration Word Addresses 12 PIC24FJ16GA 002BFEh 002BFCh PIC24FJ32GA 0057FEh 0057FCh PIC24FJ48GA 0083FEh 0083FCh PIC24FJ64GA 00ABFEh 00ABFCh PIC24FJ96GA 00FFFEh 00FFFCh PIC24FJ128GAGA 0157FEh 0157FCh Device User Memory Address Limit (Instruction Words) Write Blocks Erase Blocks PIC24FJ16GA 002BFEh (5.5K) 88 11 PIC24FJ32GA 0057FEh (11K) 176 22 PIC24FJ48GA 0083FEh (16.5K) 264 33 PIC24FJ64GA 00ABFEh (22K) 344 43 PIC24FJ96GA 00FFFEh (32K) 512 64 PIC24FJ128GA 0157FEh (44K) 688 86 |
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